The PWR block was merged into the SMUIO block by revision 12 so we add that to the smuio_12_0_0 headers. (v2): Drop nonsensical smuio_10_0_0 header Signed-off-by: Tom St Denis <tom.stdenis@xxxxxxx> --- .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++ .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h index 327b4d09f66d..9bf73284ad73 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h @@ -24,4 +24,7 @@ #define mmSMUIO_GFX_MISC_CNTL 0x00c8 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0 +#define mmPWR_MISC_CNTL_STATUS 0x0183 +#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 1 + #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h index d815452cfd15..26556fa3d054 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h @@ -24,5 +24,10 @@ //SMUIO_GFX_MISC_CNTL #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1 +//PWR_MISC_CNTL_STATUS +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L #endif -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
