RE: [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range

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> -----Original Message-----
> From: Bjorn Helgaas <helgaas@xxxxxxxxxx>
> Sent: Monday, March 9, 2020 9:11 PM
> To: Liang, Prike <Prike.Liang@xxxxxxx>
> Cc: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Quan, Evan <Evan.Quan@xxxxxxx>;
> Huang, Ray <Ray.Huang@xxxxxxx>; linux-kernel@xxxxxxxx; Deucher,
> Alexander <Alexander.Deucher@xxxxxxx>
> Subject: Re: [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for
> setting clock range
> 
> On Wed, Mar 04, 2020 at 10:55:37AM +0800, Prike Liang wrote:
> > This fix will handle some MP1 FW issue like as mclk dpm table in
> > renoir has a reverse dpm clock layout and a zero frequency dpm level
> > as following case.
> >
> > cat pp_dpm_mclk
> > 0: 1200Mhz
> > 1: 1200Mhz
> > 2: 800Mhz
> > 3: 0Mhz
> >
> > Signed-off-by: Prike Liang <Prike.Liang@xxxxxxx>
> > ---
> >  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
> > drivers/gpu/drm/amd/powerplay/smu_v12_0.c  | 3 ---
> >  2 files changed, 1 insertion(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > index e3398f9..d454493 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > @@ -214,7 +214,7 @@ int smu_set_soft_freq_range(struct smu_context
> > *smu, enum smu_clk_type clk_type,  {
> >  	int ret = 0;
> >
> > -	if (min <= 0 && max <= 0)
> > +	if (min < 0 && max < 0)
> 
> This change causes the following Coverity warning because min and max are
> both unsigned:
> 
> int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type
> clk_type,
>                             uint32_t min, uint32_t max)
> 
> >>>     CID 1460516:  Integer handling issues  (NO_EFFECT)
> >>>     This less-than-zero comparison of an unsigned value is never true.
> "min < 0U".
[Prike] Thanks and will fix the Coverity warning. 
> 225             if (min < 0 && max < 0)
> 226                     return -EINVAL;
> 
> >  		return -EINVAL;
> >
> >  	if (!smu_clk_dpm_is_enabled(smu, clk_type))
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