On Thu, Feb 27, 2020 at 10:54 AM Hersen Wu <hersenxs.wu@xxxxxxx> wrote:
>
> This interface is for dGPU Navi1x. Linux dc-pplib interface depends
> on window driver dc implementation.
>
> For Navi1x, clock settings of dcn watermarks are fixed. the settings
> should be passed to smu during boot up and resume from s3.
> boot up: dc calculate dcn watermark clock settings within dc_create,
> dcn20_resource_construct, then call pplib functions below to pass
> the settings to smu:
> smu_set_watermarks_for_clock_ranges
> smu_set_watermarks_table
> navi10_set_watermarks_table
> smu_write_watermarks_table
>
> For Renoir, clock settings of dcn watermark are also fixed values.
> dc has implemented different flow for window driver:
> dc_hardware_init / dc_set_power_state
> dcn10_init_hw
> notify_wm_ranges
> set_wm_ranges
>
> For Linux
> smu_set_watermarks_for_clock_ranges
> renoir_set_watermarks_table
> smu_write_watermarks_table
>
> dc_hardware_init -> amdgpu_dm_init
> dc_set_power_state --> dm_resume
>
> therefore, linux dc-pplib interface of navi10/12/14 is different
> from that of Renoir.
>
> Signed-off-by: Hersen Wu <hersenxs.wu@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64 +++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 931cbd7b372e..c58c0e95735e 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1435,6 +1435,68 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend)
> drm_kms_helper_hotplug_event(dev);
> }
>
> +static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
> +{
> + struct smu_context *smu = &adev->smu;
> + int ret = 0;
> +
> + if (!is_support_sw_smu(adev))
> + return 0;
> +
> + /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
> + * on window driver dc implementation.
> + * For Navi1x, clock settings of dcn watermarks are fixed. the settings
> + * should be passed to smu during boot up and resume from s3.
> + * boot up: dc calculate dcn watermark clock settings within dc_create,
> + * dcn20_resource_construct
> + * then call pplib functions below to pass the settings to smu:
> + * smu_set_watermarks_for_clock_ranges
> + * smu_set_watermarks_table
> + * navi10_set_watermarks_table
> + * smu_write_watermarks_table
> + *
> + * For Renoir, clock settings of dcn watermark are also fixed values.
> + * dc has implemented different flow for window driver:
> + * dc_hardware_init / dc_set_power_state
> + * dcn10_init_hw
> + * notify_wm_ranges
> + * set_wm_ranges
> + * -- Linux
> + * smu_set_watermarks_for_clock_ranges
> + * renoir_set_watermarks_table
> + * smu_write_watermarks_table
> + *
> + * For Linux,
> + * dc_hardware_init -> amdgpu_dm_init
> + * dc_set_power_state --> dm_resume
> + *
> + * therefore, this function apply to navi10/12/14 but not Renoir
> + * *
> + */
> + switch(adev->asic_type) {
> + case CHIP_NAVI10:
> + case CHIP_NAVI14:
> + case CHIP_NAVI12:
> + break;
> + default:
> + return 0;
> + }
> +
> + /* pass data to smu controller */
> + if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
> + !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
> + ret = smu_write_watermarks_table(smu);
> +
> + if (ret) {
> + DRM_ERROR("Failed to update WMTABLE!\n");
> + return ret;
> + }
> + smu->watermarks_bitmap |= WATERMARKS_LOADED;
> + }
> +
> + return 0;
> +}
> +
> /**
> * dm_hw_init() - Initialize DC device
> * @handle: The base driver device containing the amdgpu_dm device.
> @@ -1713,6 +1775,8 @@ static int dm_resume(void *handle)
>
> amdgpu_dm_irq_resume_late(adev);
>
> + amdgpu_dm_smu_write_watermarks_table(adev);
> +
> return 0;
> }
>
> --
> 2.17.1
>
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