Re: [PATCH 4/6] drm/amdgpu/vcn2.5: add dpg pause mode

[James Zhu <jamesz@xxxxxxx>]

On 2020-01-14 2:10 p.m., Leo Liu wrote:
> On 2020-01-14 12:58 p.m., James Zhu wrote:
> > Add dpg pause mode support for vcn2.5
> >
> > Signed-off-by: James Zhu <James.Zhu@xxxxxxx>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 70 
> > +++++++++++++++++++++++++++++++++++
> >   1 file changed, 70 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 
> > b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> > index ea70aa8..8de51c9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> > @@ -60,6 +60,8 @@ static void vcn_v2_5_set_enc_ring_funcs(struct 
> > amdgpu_device *adev);
> >   static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
> >   static int vcn_v2_5_set_powergating_state(void *handle,
> >                   enum amd_powergating_state state);
> > +static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
> > +                int inst_idx, struct dpg_pause_state *new_state);
> >   static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
> >     static int amdgpu_ih_clientid_vcns[] = {
> > @@ -217,6 +219,9 @@ static int vcn_v2_5_sw_init(void *handle)
> >               return r;
> >       }
> >   +    if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> > +        adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode;
> > +
> >       return 0;
> >   }
> >   @@ -1327,6 +1332,67 @@ static int vcn_v2_5_stop(struct 
> > amdgpu_device *adev)
> >       return 0;
> >   }
> >   +static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
> > +                int inst_idx, struct dpg_pause_state *new_state)
>
> I think here is the same thing, add instance to v2_0, and avoid the 
> duplication.
vcn2.5 and vcn2.0 are not exactly the same.

James

> Regards,
>
> Leo
>
>
> > +{
> > +    struct amdgpu_ring *ring;
> > +    uint32_t reg_data = 0;
> > +    int ret_code;
> > +
> > +    /* pause/unpause if state is changed */
> > +    if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
> > +        DRM_DEBUG("dpg pause state changed %d -> %d",
> > +            adev->vcn.pause_state.fw_based, new_state->fw_based);
> > +        reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) &
> > +            (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
> > +
> > +        if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
> > +            ret_code = 0;
> > +            SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 0x1,
> > +                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
> > +
> > +            if (!ret_code) {
> > +                /* pause DPG */
> > +                reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);
> > +
> > +                /* wait for ACK */
> > +                SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_DPG_PAUSE,
> > +                       UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
> > +                       UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
> > +
> > +                /* Restore */
> > +                ring = &adev->vcn.inst[inst_idx].ring_enc[0];
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO, 
> > ring->gpu_addr);
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI, 
> > upper_32_bits(ring->gpu_addr));
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE, 
> > ring->ring_size / 4);
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RB_RPTR, 
> > lower_32_bits(ring->wptr));
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR, 
> > lower_32_bits(ring->wptr));
> > +
> > +                ring = &adev->vcn.inst[inst_idx].ring_enc[1];
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO2, 
> > ring->gpu_addr);
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI2, 
> > upper_32_bits(ring->gpu_addr));
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE2, 
> > ring->ring_size / 4);
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RB_RPTR2, 
> > lower_32_bits(ring->wptr));
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR2, 
> > lower_32_bits(ring->wptr));
> > +
> > +                WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,
> > +                       RREG32_SOC15(UVD, inst_idx, mmUVD_SCRATCH2) & 
> > 0x7FFFFFFF);
> > +
> > +                SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS,
> > +                       0x0, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, 
> > ret_code);
> > +            }
> > +        } else {
> > +            /* unpause dpg, no need to wait */
> > +            reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
> > +            WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);
> > +        }
> > +        adev->vcn.pause_state.fw_based = new_state->fw_based;
> > +    }
> > +
> > +    return 0;
> > +}
> > +
> >   /**
> >    * vcn_v2_5_dec_ring_get_rptr - get read pointer
> >    *
> > @@ -1369,6 +1435,10 @@ static void vcn_v2_5_dec_ring_set_wptr(struct 
> > amdgpu_ring *ring)
> >   {
> >       struct amdgpu_device *adev = ring->adev;
> >   +    if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> > +        WREG32_SOC15(UVD, ring->me, mmUVD_SCRATCH2,
> > +            lower_32_bits(ring->wptr) | 0x80000000);
> > +
> >       if (ring->use_doorbell) {
> >           adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
> >           WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
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