DP 1.4a specification defines Link Training Tunable PHY Repeater (LTTPR) which is required to add support for systems with Thunderbolt or other repeater devices. Changes since V1: - Adjusts registers names to be aligned with spec and the rest of the file - Update spec comment from 1.4 to 1.4a Cc: Abdoulaye Berthe <Abdoulaye.Berthe@xxxxxxx> Cc: Harry Wentland <harry.wentland@xxxxxxx> Cc: Leo Li <sunpeng.li@xxxxxxx> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@xxxxxxx> Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe@xxxxxxx> --- include/drm/drm_dp_helper.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8364502f92cf..e8beb4e7e5da 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -134,6 +134,31 @@ #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ +/** Link Training (LT)-tunable Physical Repeaters - DP 1.4a **/ +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 +#define DP_PHY_REPEATER_CNT 0xf0002 +#define DP_PHY_REPEATER_MODE 0xf0003 +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 +#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 +#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 +#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 +#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 +#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 +#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 +#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 +#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 +#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 +#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 +#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 + /* Multiple stream transport */ #define DP_FAUX_CAP 0x020 /* 1.2 */ # define DP_FAUX_CAP_1 (1 << 0) -- 2.23.0
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