Am 09.08.19 um 04:15 schrieb Zeng, Oak:
> Add definition of all supported mtypes. The RW mtype
> is recently introduced for arcturus. Also add definition
> of a flag to probe and possibly invalidate remote GPU
> cache, which will be used later in this series.
>
> Change-Id: I96fc9bb4b6b1e62bdc10b600d8aaa6a802128d6d
> Signed-off-by: Oak Zeng <Oak.Zeng@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 9 +++++++--
> include/uapi/drm/amdgpu_drm.h | 4 ++++
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 2eda3a8..7a77477 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -80,8 +80,13 @@ struct amdgpu_bo_list_entry;
> #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57)
> #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL)
>
> -#define AMDGPU_MTYPE_NC 0
> -#define AMDGPU_MTYPE_CC 2
> +enum amdgpu_mtype {
> + AMDGPU_MTYPE_NC = 0,
> + AMDGPU_MTYPE_WC = 1,
> + AMDGPU_MTYPE_CC = 2,
> + AMDGPU_MTYPE_UC = 3,
> + AMDGPU_MTYPE_RW = 4,
> +};
Mhm, why an enum?
Christian.
>
> #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
> | AMDGPU_PTE_SNOOPED \
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index ca97b68..97e8e51 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -503,6 +503,10 @@ struct drm_amdgpu_gem_op {
> #define AMDGPU_VM_MTYPE_CC (3 << 5)
> /* Use UC MTYPE instead of default MTYPE */
> #define AMDGPU_VM_MTYPE_UC (4 << 5)
> +/* Use RW MTYPE instead of default MTYPE */
> +#define AMDGPU_VM_MTYPE_RW (5 << 5)
> +/* Cacheable/snoopable */
> +#define AMDGPU_VM_PAGE_INVALIDATE_PROBE (1 << 9)
>
> struct drm_amdgpu_gem_va {
> /** GEM object handle */
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