Eric's right. For now, we have a function that is a generic isDPMAvailable, that checks for the presence of the "dpm_state" sysfs file. In this case if we only have 1 clock available, it will just report that one clock for all outputs. So the SMI can handle this effectively. Thanks for checking though Felix, I definitely appreciate it. Kent > -----Original Message----- > From: Huang, JinHuiEric > Sent: Tuesday, February 19, 2019 2:58 PM > To: Kuehling, Felix <Felix.Kuehling@xxxxxxx>; amd- > gfx@xxxxxxxxxxxxxxxxxxxxx; Russell, Kent <Kent.Russell@xxxxxxx> > Subject: Re: [PATCH] drm/powerplay: Get fix clock info when dpm is disabled > for the clock > > "rocm-smi -s" doesn't parse output from driver and it directly display output, > so it will not break rocm-smi. > > Regards, > > Eric > > On 2019-02-19 2:51 p.m., Kuehling, Felix wrote: > > [+Kent] > > > > On 2019-02-19 12:08 p.m., Huang, JinHuiEric wrote: > > > >> It seems redundant to print out all DPM levels when DPM is disabled. > >> Probably it looks meaningful to print out "<current clock>Mhz (DPM > >> disabled)". > > If you change the format, you risk breaking tools such as rocm-smi. Is > > there some other way for rocm-smi to tell that DPM is disabled? > > > > Regards, > > Felix > > > > > >> Regards, > >> > >> Eric > >> > >> On 2019-02-15 4:25 p.m., Liu, Shaoyun wrote: > >>> When DPM for the specific clock is difabled, driver should still > >>> able to get fix clock info from the pptable > >>> > >>> Change-Id: Ic609203b3b87aa75b0cfd57b57717b3bb89daf48 > >>> Signed-off-by: shaoyunl <shaoyun.liu@xxxxxxx> > >>> --- > >>> drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 16 ------- > --------- > >>> 1 file changed, 16 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c > >>> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c > >>> index aad79aff..2eae0b4 100644 > >>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c > >>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c > >>> @@ -2641,10 +2641,6 @@ static int vega20_get_sclks(struct pp_hwmgr > *hwmgr, > >>> struct vega20_single_dpm_table *dpm_table = &(data- > >dpm_table.gfx_table); > >>> int i, count; > >>> > >>> - PP_ASSERT_WITH_CODE(data- > >smu_features[GNLD_DPM_GFXCLK].enabled, > >>> - "[GetSclks]: gfxclk dpm not enabled!\n", > >>> - return -EPERM); > >>> - > >>> count = (dpm_table->count > MAX_NUM_CLOCKS) ? > MAX_NUM_CLOCKS : dpm_table->count; > >>> clocks->num_levels = count; > >>> > >>> @@ -2670,10 +2666,6 @@ static int vega20_get_memclocks(struct > pp_hwmgr *hwmgr, > >>> struct vega20_single_dpm_table *dpm_table = &(data- > >dpm_table.mem_table); > >>> int i, count; > >>> > >>> - PP_ASSERT_WITH_CODE(data- > >smu_features[GNLD_DPM_UCLK].enabled, > >>> - "[GetMclks]: uclk dpm not enabled!\n", > >>> - return -EPERM); > >>> - > >>> count = (dpm_table->count > MAX_NUM_CLOCKS) ? > MAX_NUM_CLOCKS : dpm_table->count; > >>> clocks->num_levels = data->mclk_latency_table.count = count; > >>> > >>> @@ -2696,10 +2688,6 @@ static int vega20_get_dcefclocks(struct > pp_hwmgr *hwmgr, > >>> struct vega20_single_dpm_table *dpm_table = &(data- > >dpm_table.dcef_table); > >>> int i, count; > >>> > >>> - PP_ASSERT_WITH_CODE(data- > >smu_features[GNLD_DPM_DCEFCLK].enabled, > >>> - "[GetDcfclocks]: dcefclk dpm not enabled!\n", > >>> - return -EPERM); > >>> - > >>> count = (dpm_table->count > MAX_NUM_CLOCKS) ? > MAX_NUM_CLOCKS : dpm_table->count; > >>> clocks->num_levels = count; > >>> > >>> @@ -2719,10 +2707,6 @@ static int vega20_get_socclocks(struct > pp_hwmgr *hwmgr, > >>> struct vega20_single_dpm_table *dpm_table = &(data- > >dpm_table.soc_table); > >>> int i, count; > >>> > >>> - PP_ASSERT_WITH_CODE(data- > >smu_features[GNLD_DPM_SOCCLK].enabled, > >>> - "[GetSocclks]: socclk dpm not enabled!\n", > >>> - return -EPERM); > >>> - > >>> count = (dpm_table->count > MAX_NUM_CLOCKS) ? > MAX_NUM_CLOCKS : dpm_table->count; > >>> clocks->num_levels = count; > >>> > >> _______________________________________________ > >> amd-gfx mailing list > >> amd-gfx@xxxxxxxxxxxxxxxxxxxxx > >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
