I've since replaced the LS1012ARDB with a LS1046ARDB, and this works out of the box.
The LS1012ARDB does not have an SMMU, which handles hardware coherency on ARM.
So amdgpu won't work on any ARM without an SMMU.
Bas Vermeulen
On Thu, Jan 10, 2019 at 2:38 PM Koenig, Christian <Christian.Koenig@xxxxxxx> wrote:
Am 10.01.19 um 14:31 schrieb Bas Vermeulen:
On Thu, Jan 10, 2019 at 11:59 AM Christian König <ckoenig.leichtzumerken@xxxxxxxxx> wrote:
The PCI Express controller as instantiated on this chip does not support hardware coherency. All incoming PCI Express transactions are made non IO-coherent.
Would AMDGPU still work with that PCI Express controller, or is this a show-stopper?
I'm really wondering what this comment in the documentation means.
As far as I know PCIe doesn't support cache coherency in the downstream and supporting it in the up stream is a must have.
So what exactly is meant here with IO-coherent?
I believe IO Coherent means that when PCIe writes something to CPU memory, the caches are flushed or updated
(or in this case they aren't). I found https://community.arm.com/processors/b/blog/posts/extended-system-coherency---part-1---cache-coherency-fundamentalswith this explanation.
Yeah, but as I said this upstream memory coherency is mandatory for PCIe.
When a controller doesn't have that it can't call itself a PCIe controller. The spec is pretty clear about that :)
And to answer the original question: Yes, that would be a totally show-stopper.
Regards,
Christian.
Regards,
Bas Vermeulen
_______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
