Re: Trying to run AMD E9260 (Polaris 11) on NXP LS1012A-RDB

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On Thu, Jan 10, 2019 at 11:59 AM Christian König <ckoenig.leichtzumerken@xxxxxxxxx> wrote:
The PCI Express controller as instantiated on this chip does not support hardware coherency. All incoming PCI Express transactions are made non IO-coherent.

Would AMDGPU still work with that PCI Express controller, or is this a show-stopper?

I'm really wondering what this comment in the documentation means.

As far as I know PCIe doesn't support cache coherency in the downstream and supporting it in the up stream is a must have.
So what exactly is meant here with IO-coherent?

I believe IO Coherent means that when PCIe writes something to CPU memory, the caches are flushed or updated
(or in this case they aren't). I found https://community.arm.com/processors/b/blog/posts/extended-system-coherency---part-1---cache-coherency-fundamentals 
with this explanation.

Regards,

Bas Vermeulen
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