[PATCH 4/4] drm/amdgpu: add psp firmware loading for vcn

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On Thu, Aug 9, 2018 at 11:41 AM, James Zhu <jzhums at gmail.com> wrote:
> Signed-off-by: James Zhu <James.Zhu at amd.com>

Please include a patch description. E.g., update VCN code to handle
firmware loading via the psp.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +++++++++------
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 ++++++++++++++++++++++++++-------
>  2 files changed, 40 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 798648a..290d558 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
>                         version_major, version_minor, family_id);
>         }
>
> -       bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
> -                 +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
> +       bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
>                   +  AMDGPU_VCN_SESSION_SIZE * 40;
> +       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> +               bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>         r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
>                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
>                                     &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
> @@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
>                 unsigned offset;
>
>                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> -               offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> -               memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
> -                           le32_to_cpu(hdr->ucode_size_bytes));
> -               size -= le32_to_cpu(hdr->ucode_size_bytes);
> -               ptr += le32_to_cpu(hdr->ucode_size_bytes);
> +               if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> +                       offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> +                       memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
> +                                   le32_to_cpu(hdr->ucode_size_bytes));
> +                       size -= le32_to_cpu(hdr->ucode_size_bytes);
> +                       ptr += le32_to_cpu(hdr->ucode_size_bytes);
> +               }
>                 memset_io(ptr, 0, size);
>         }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 4678248..775201d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -100,6 +100,16 @@ static int vcn_v1_0_sw_init(void *handle)
>         if (r)
>                 return r;
>
> +       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +               const struct common_firmware_header *hdr;
> +               hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> +               adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
> +               adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> +               adev->firmware.fw_size +=
> +                       ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> +               DRM_INFO("PSP loading VCN firmware\n");
> +       }
> +
>         r = amdgpu_vcn_resume(adev);
>         if (r)
>                 return r;
> @@ -265,26 +275,38 @@ static int vcn_v1_0_resume(void *handle)
>  static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
>  {
>         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
> -
> -       WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> +       uint32_t offset;
> +
> +       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> +                       (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
> +               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> +                       (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
> +               WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
> +               offset = 0;
> +       } else {
> +               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
>                         lower_32_bits(adev->vcn.gpu_addr));
> -       WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> +               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
>                         upper_32_bits(adev->vcn.gpu_addr));
> -       WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
> +               offset = size;
> +               WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
>                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
> +       }
> +
>         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
>
>         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
> -                       lower_32_bits(adev->vcn.gpu_addr + size));
> +                       lower_32_bits(adev->vcn.gpu_addr + offset));
>         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
> -                       upper_32_bits(adev->vcn.gpu_addr + size));
> +                       upper_32_bits(adev->vcn.gpu_addr + offset));
>         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
>         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE);
>
>         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
> -                       lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
> +                       lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
>         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
> -                       upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
> +                       upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
>         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
>         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
>                         AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40));
> --
> 2.7.4
>
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> amd-gfx at lists.freedesktop.org
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