Am 15.03.2018 um 07:12 schrieb Feifei Xu:
> From: Hawking Zhang <Hawking.Zhang at amd.com>
>
> Change-Id: I09f9ddea0ad23af00fadd9af7aaccf7160e4e569
> Signed-off-by: Hawking Zhang <Hawking.Zhang at amd.com>
> Acked-by: John Bridgman <john.bridgman at amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Feifei Xu <Feifei.Xu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 19 +++++++++++++++----
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 19 +++++++++++++++----
> 2 files changed, 30 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 0d72f52..3689f1d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -71,10 +71,21 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
> {
> uint64_t value;
>
> - /* Disable AGP. */
> - WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
> - WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
> - WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF);
> + if (adev->gmc.zfb_size > 0) {
> + /* Disable LFB */
> + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
> + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
> +
> + /* Enable AGP */
> + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, adev->gmc.zfb_phys_addr >> 24);
> + WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.vram_end >> 24);
> + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.vram_start >> 24);
> + } else {
> + /* Disable AGP. */
> + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
> + WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
> + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF);
> + }
>
> /* Program the system aperture low logical page number. */
> WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index bd3777a..ef79d49 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -82,10 +82,21 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
> uint64_t value;
> uint32_t tmp;
>
> - /* Disable AGP. */
> - WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
> - WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
> - WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF);
> + if (adev->gmc.zfb_size > 0) {
> + /* Disable LFB */
> + WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 0);
> + WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
> +
> + /* Enable AGP */
> + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, adev->gmc.zfb_phys_addr >> 24);
> + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.vram_end >> 24);
> + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.vram_start >> 24);
> + } else {
> + /* Disable AGP. */
> + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
> + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
> + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF);
> + }
>
> /* Program the system aperture low logical page number. */
> WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
