[PATCH 6/8] drm/amdgpu: enable physical transaction for ptd/pde when ZFB is enabled

[ckoenig.leichtzumerken@xxxxxxxxx (Christian König)]

Am 15.03.2018 um 07:12 schrieb Feifei Xu:
> Change-Id: I2b45d765f1f60252fa1c02aced94f8100d575ddc
> Signed-off-by: Hawking Zhang <Hawking.Zhang at amd.com>
> Signed-off-by: Feifei Xu <Feifei.Xu at amd.com>
> Acked-by: John Bridgman <john.bridgman at amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

There is a typo in the subject, apart from that the patch is 
Reviewed-by: Christian König <christian.koenig at amd.com>.

Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 9 +++++++--
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 9 +++++++--
>   2 files changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index acfbd2d..0d72f52 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -155,8 +155,13 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
>   	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
>   
>   	tmp = mmVM_L2_CNTL4_DEFAULT;
> -	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
> -	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
> +	if (adev->gmc.zfb_size > 0) {
> +		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
> +		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
> +	} else {
> +		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
> +		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
> +	}
>   	WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);
>   }
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 3dd5816..bd3777a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -166,8 +166,13 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
>   	}
>   
>   	tmp = mmVM_L2_CNTL4_DEFAULT;
> -	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
> -	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
> +	if (adev->gmc.zfb_size > 0) {
> +		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
> +		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
> +	} else {
> +		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
> +		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
> +	}
>   	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
>   }
>