Hi, In my attempt to add the code for dce6 in dc (I base myself on dce80 code), it seems I miss the mmDPREFCLK_CNTL (dc/dce/dce_clocks.h) register description for dce60. I have mmDENTIST_DISPCLK_CNTL though. I miss too the "max_clks_by_state" per power state limits (dc/dce/dce_clocks.c) for dce60 as I could not find any in amdgpu direct display code. A wild guess would be those limits are the same than those for dce80. More I get into DC code, more I get puzzled about what benefits would bring DC code for the current dce60 hardware: Is dce60 _really_ able to do DP adaptive sync (freesync)? regards, -- Sylvain
