Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
---
src/lib/ip/dce120_bits.i | 7 +
src/lib/ip/dce120_regs.i | 2 +
src/lib/ip/gfx90_bits.i | 33 --
src/lib/ip/gfx90_regs.i | 7 -
src/lib/ip/hdp40_bits.i | 242 --------------
src/lib/ip/mp90_bits.i | 176 -----------
src/lib/ip/sdma040_bits.i | 783 ----------------------------------------------
src/lib/ip/sdma140_bits.i | 764 --------------------------------------------
src/lib/ip/smu713_bits.i | 4 +
src/lib/ip/smu713_regs.i | 1 +
10 files changed, 14 insertions(+), 2005 deletions(-)
diff --git a/src/lib/ip/dce120_bits.i b/src/lib/ip/dce120_bits.i
index d1ad62fdba35..a1a88c89c66b 100644
--- a/src/lib/ip/dce120_bits.i
+++ b/src/lib/ip/dce120_bits.i
@@ -5901,6 +5901,13 @@ static struct umr_bitfield mmDCIO_WRCMD_DELAY[] = {
{ "DCRXPHY_DELAY", 12, 15, &umr_bitfield_default },
{ "ZCAL_DELAY", 16, 19, &umr_bitfield_default },
};
+static struct umr_bitfield mmDC_PINSTRAPS[] = {
+ { "DC_PINSTRAPS_AUDIO", 14, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_DC_MISC_STRAPS[] = {
+ { "HDMI_DISABLE", 6, 6, &umr_bitfield_default },
+ { "AUDIO_STREAM_NUMBER", 8, 10, &umr_bitfield_default },
+};
static struct umr_bitfield mmDC_DVODATA_CONFIG[] = {
{ "VIP_MUX_EN", 19, 19, &umr_bitfield_default },
{ "VIP_ALTER_MAPPING_EN", 20, 20, &umr_bitfield_default },
diff --git a/src/lib/ip/dce120_regs.i b/src/lib/ip/dce120_regs.i
index 8cfcb36681bd..873e9a8606f9 100644
--- a/src/lib/ip/dce120_regs.i
+++ b/src/lib/ip/dce120_regs.i
@@ -880,6 +880,8 @@
{ "mmUNIPHYG_LINK_CNTL", REG_MMIO, 0x208f, 2, &mmUNIPHYG_LINK_CNTL[0], sizeof(mmUNIPHYG_LINK_CNTL)/sizeof(mmUNIPHYG_LINK_CNTL[0]), 0, 0 },
{ "mmUNIPHYG_CHANNEL_XBAR_CNTL", REG_MMIO, 0x2090, 2, &mmUNIPHYG_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYG_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYG_CHANNEL_XBAR_CNTL[0]), 0, 0 },
{ "mmDCIO_WRCMD_DELAY", REG_MMIO, 0x2094, 2, &mmDCIO_WRCMD_DELAY[0], sizeof(mmDCIO_WRCMD_DELAY)/sizeof(mmDCIO_WRCMD_DELAY[0]), 0, 0 },
+ { "mmDC_PINSTRAPS", REG_MMIO, 0x2096, 2, &mmDC_PINSTRAPS[0], sizeof(mmDC_PINSTRAPS)/sizeof(mmDC_PINSTRAPS[0]), 0, 0 },
+ { "mmCC_DC_MISC_STRAPS", REG_MMIO, 0x2097, 2, &mmCC_DC_MISC_STRAPS[0], sizeof(mmCC_DC_MISC_STRAPS)/sizeof(mmCC_DC_MISC_STRAPS[0]), 0, 0 },
{ "mmDC_DVODATA_CONFIG", REG_MMIO, 0x2098, 2, &mmDC_DVODATA_CONFIG[0], sizeof(mmDC_DVODATA_CONFIG)/sizeof(mmDC_DVODATA_CONFIG[0]), 0, 0 },
{ "mmLVTMA_PWRSEQ_CNTL", REG_MMIO, 0x2099, 2, &mmLVTMA_PWRSEQ_CNTL[0], sizeof(mmLVTMA_PWRSEQ_CNTL)/sizeof(mmLVTMA_PWRSEQ_CNTL[0]), 0, 0 },
{ "mmLVTMA_PWRSEQ_STATE", REG_MMIO, 0x209a, 2, &mmLVTMA_PWRSEQ_STATE[0], sizeof(mmLVTMA_PWRSEQ_STATE)/sizeof(mmLVTMA_PWRSEQ_STATE[0]), 0, 0 },
diff --git a/src/lib/ip/gfx90_bits.i b/src/lib/ip/gfx90_bits.i
index e0008b2f93ae..029a54f6a941 100644
--- a/src/lib/ip/gfx90_bits.i
+++ b/src/lib/ip/gfx90_bits.i
@@ -2864,12 +2864,6 @@ static struct umr_bitfield mmTA_CNTL_AUX[] = {
static struct umr_bitfield mmTA_RESERVED_010C[] = {
{ "Unused", 0, 31, &umr_bitfield_default },
};
-static struct umr_bitfield mmTA_GRAD_ADJ[] = {
- { "GRAD_ADJ_0", 0, 7, &umr_bitfield_default },
- { "GRAD_ADJ_1", 8, 15, &umr_bitfield_default },
- { "GRAD_ADJ_2", 16, 23, &umr_bitfield_default },
- { "GRAD_ADJ_3", 24, 31, &umr_bitfield_default },
-};
static struct umr_bitfield mmTA_STATUS[] = {
{ "FG_PFIFO_EMPTYB", 12, 12, &umr_bitfield_default },
{ "FG_LFIFO_EMPTYB", 13, 13, &umr_bitfield_default },
@@ -9574,9 +9568,6 @@ static struct umr_bitfield mmDB_DFSM_CONTROL[] = {
{ "POPS_DRAIN_PS_ON_OVERLAP", 2, 2, &umr_bitfield_default },
{ "DISALLOW_OVERFLOW", 3, 3, &umr_bitfield_default },
};
-static struct umr_bitfield mmDB_RENDER_FILTER[] = {
- { "PS_INVOKE_MASK", 0, 15, &umr_bitfield_default },
-};
static struct umr_bitfield mmDB_Z_INFO2[] = {
{ "EPITCH", 0, 15, &umr_bitfield_default },
};
@@ -9973,7 +9964,6 @@ static struct umr_bitfield mmPA_SC_TILE_STEERING_OVERRIDE[] = {
{ "ENABLE", 0, 0, &umr_bitfield_default },
{ "NUM_SE", 1, 2, &umr_bitfield_default },
{ "NUM_RB_PER_SE", 5, 6, &umr_bitfield_default },
- { "DISABLE_SRBSL_DB_OPTIMIZED_PACKING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmCP_PERFMON_CNTX_CNTL[] = {
{ "PERFMON_ENABLE", 31, 31, &umr_bitfield_default },
@@ -10005,16 +9995,6 @@ static struct umr_bitfield mmPA_SC_HORIZ_GRID[] = {
{ "BOT_HALF", 16, 23, &umr_bitfield_default },
{ "BOT_QTR", 24, 31, &umr_bitfield_default },
};
-static struct umr_bitfield mmPA_SC_FOV_WINDOW_LR[] = {
- { "LEFT_EYE_FOV_LEFT", 0, 7, &umr_bitfield_default },
- { "LEFT_EYE_FOV_RIGHT", 8, 15, &umr_bitfield_default },
- { "RIGHT_EYE_FOV_LEFT", 16, 23, &umr_bitfield_default },
- { "RIGHT_EYE_FOV_RIGHT", 24, 31, &umr_bitfield_default },
-};
-static struct umr_bitfield mmPA_SC_FOV_WINDOW_TB[] = {
- { "FOV_TOP", 0, 7, &umr_bitfield_default },
- { "FOV_BOT", 8, 15, &umr_bitfield_default },
-};
static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_INDX[] = {
{ "RESET_INDX", 0, 31, &umr_bitfield_default },
};
@@ -11346,7 +11326,6 @@ static struct umr_bitfield mmPA_SU_SMALL_PRIM_FILTER_CNTL[] = {
{ "LINE_FILTER_DISABLE", 2, 2, &umr_bitfield_default },
{ "POINT_FILTER_DISABLE", 3, 3, &umr_bitfield_default },
{ "RECTANGLE_FILTER_DISABLE", 4, 4, &umr_bitfield_default },
- { "SRBSL_ENABLE", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmPA_CL_OBJPRIM_ID_CNTL[] = {
{ "OBJ_ID_SEL", 0, 0, &umr_bitfield_default },
@@ -11575,9 +11554,6 @@ static struct umr_bitfield mmVGT_DRAW_PAYLOAD_CNTL[] = {
{ "EN_PIPELINE_PRIMID", 2, 2, &umr_bitfield_default },
{ "OBJECT_ID_INST_EN", 3, 3, &umr_bitfield_default },
};
-static struct umr_bitfield mmVGT_INDEX_PAYLOAD_CNTL[] = {
- { "COMPOUND_INDEX_EN", 0, 0, &umr_bitfield_default },
-};
static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_0[] = {
{ "STEP_RATE", 0, 31, &umr_bitfield_default },
};
@@ -13448,9 +13424,6 @@ static struct umr_bitfield mmIA_MULTI_VGT_PARAM[] = {
{ "EN_INST_OPT_ADV", 22, 22, &umr_bitfield_default },
{ "HW_USE_ONLY", 23, 23, &umr_bitfield_default },
};
-static struct umr_bitfield mmVGT_OBJECT_ID[] = {
- { "REG_OBJ_ID", 0, 31, &umr_bitfield_default },
-};
static struct umr_bitfield mmVGT_INSTANCE_BASE_ID[] = {
{ "INSTANCE_BASE_ID", 0, 31, &umr_bitfield_default },
};
@@ -13623,12 +13596,6 @@ static struct umr_bitfield mmTA_CS_BC_BASE_ADDR[] = {
static struct umr_bitfield mmTA_CS_BC_BASE_ADDR_HI[] = {
{ "ADDRESS", 0, 7, &umr_bitfield_default },
};
-static struct umr_bitfield mmTA_GRAD_ADJ_UCONFIG[] = {
- { "GRAD_ADJ_0", 0, 7, &umr_bitfield_default },
- { "GRAD_ADJ_1", 8, 15, &umr_bitfield_default },
- { "GRAD_ADJ_2", 16, 23, &umr_bitfield_default },
- { "GRAD_ADJ_3", 24, 31, &umr_bitfield_default },
-};
static struct umr_bitfield mmDB_OCCLUSION_COUNT0_LOW[] = {
{ "COUNT_LOW", 0, 31, &umr_bitfield_default },
};
diff --git a/src/lib/ip/gfx90_regs.i b/src/lib/ip/gfx90_regs.i
index fad4cf307666..cd443184e17f 100644
--- a/src/lib/ip/gfx90_regs.i
+++ b/src/lib/ip/gfx90_regs.i
@@ -396,7 +396,6 @@
{ "mmTA_CNTL", REG_MMIO, 0x0541, 0, &mmTA_CNTL[0], sizeof(mmTA_CNTL)/sizeof(mmTA_CNTL[0]), 0, 0 },
{ "mmTA_CNTL_AUX", REG_MMIO, 0x0542, 0, &mmTA_CNTL_AUX[0], sizeof(mmTA_CNTL_AUX)/sizeof(mmTA_CNTL_AUX[0]), 0, 0 },
{ "mmTA_RESERVED_010C", REG_MMIO, 0x0543, 0, &mmTA_RESERVED_010C[0], sizeof(mmTA_RESERVED_010C)/sizeof(mmTA_RESERVED_010C[0]), 0, 0 },
- { "mmTA_GRAD_ADJ", REG_MMIO, 0x0544, 0, &mmTA_GRAD_ADJ[0], sizeof(mmTA_GRAD_ADJ)/sizeof(mmTA_GRAD_ADJ[0]), 0, 0 },
{ "mmTA_STATUS", REG_MMIO, 0x0548, 0, &mmTA_STATUS[0], sizeof(mmTA_STATUS)/sizeof(mmTA_STATUS[0]), 0, 0 },
{ "mmTA_SCRATCH", REG_MMIO, 0x0564, 0, &mmTA_SCRATCH[0], sizeof(mmTA_SCRATCH)/sizeof(mmTA_SCRATCH[0]), 0, 0 },
{ "mmGDS_CONFIG", REG_MMIO, 0x05c0, 0, &mmGDS_CONFIG[0], sizeof(mmGDS_CONFIG)/sizeof(mmGDS_CONFIG[0]), 0, 0 },
@@ -1601,7 +1600,6 @@
{ "mmDB_STENCIL_WRITE_BASE", REG_MMIO, 0x0016, 1, &mmDB_STENCIL_WRITE_BASE[0], sizeof(mmDB_STENCIL_WRITE_BASE)/sizeof(mmDB_STENCIL_WRITE_BASE[0]), 0, 0 },
{ "mmDB_STENCIL_WRITE_BASE_HI", REG_MMIO, 0x0017, 1, &mmDB_STENCIL_WRITE_BASE_HI[0], sizeof(mmDB_STENCIL_WRITE_BASE_HI)/sizeof(mmDB_STENCIL_WRITE_BASE_HI[0]), 0, 0 },
{ "mmDB_DFSM_CONTROL", REG_MMIO, 0x0018, 1, &mmDB_DFSM_CONTROL[0], sizeof(mmDB_DFSM_CONTROL)/sizeof(mmDB_DFSM_CONTROL[0]), 0, 0 },
- { "mmDB_RENDER_FILTER", REG_MMIO, 0x0019, 1, &mmDB_RENDER_FILTER[0], sizeof(mmDB_RENDER_FILTER)/sizeof(mmDB_RENDER_FILTER[0]), 0, 0 },
{ "mmDB_Z_INFO2", REG_MMIO, 0x001a, 1, &mmDB_Z_INFO2[0], sizeof(mmDB_Z_INFO2)/sizeof(mmDB_Z_INFO2[0]), 0, 0 },
{ "mmDB_STENCIL_INFO2", REG_MMIO, 0x001b, 1, &mmDB_STENCIL_INFO2[0], sizeof(mmDB_STENCIL_INFO2)/sizeof(mmDB_STENCIL_INFO2[0]), 0, 0 },
{ "mmTA_BC_BASE_ADDR", REG_MMIO, 0x0020, 1, &mmTA_BC_BASE_ADDR[0], sizeof(mmTA_BC_BASE_ADDR)/sizeof(mmTA_BC_BASE_ADDR[0]), 0, 0 },
@@ -1707,8 +1705,6 @@
{ "mmPA_SC_RIGHT_VERT_GRID", REG_MMIO, 0x00e8, 1, &mmPA_SC_RIGHT_VERT_GRID[0], sizeof(mmPA_SC_RIGHT_VERT_GRID)/sizeof(mmPA_SC_RIGHT_VERT_GRID[0]), 0, 0 },
{ "mmPA_SC_LEFT_VERT_GRID", REG_MMIO, 0x00e9, 1, &mmPA_SC_LEFT_VERT_GRID[0], sizeof(mmPA_SC_LEFT_VERT_GRID)/sizeof(mmPA_SC_LEFT_VERT_GRID[0]), 0, 0 },
{ "mmPA_SC_HORIZ_GRID", REG_MMIO, 0x00ea, 1, &mmPA_SC_HORIZ_GRID[0], sizeof(mmPA_SC_HORIZ_GRID)/sizeof(mmPA_SC_HORIZ_GRID[0]), 0, 0 },
- { "mmPA_SC_FOV_WINDOW_LR", REG_MMIO, 0x00eb, 1, &mmPA_SC_FOV_WINDOW_LR[0], sizeof(mmPA_SC_FOV_WINDOW_LR)/sizeof(mmPA_SC_FOV_WINDOW_LR[0]), 0, 0 },
- { "mmPA_SC_FOV_WINDOW_TB", REG_MMIO, 0x00ec, 1, &mmPA_SC_FOV_WINDOW_TB[0], sizeof(mmPA_SC_FOV_WINDOW_TB)/sizeof(mmPA_SC_FOV_WINDOW_TB[0]), 0, 0 },
{ "mmVGT_MULTI_PRIM_IB_RESET_INDX", REG_MMIO, 0x0103, 1, &mmVGT_MULTI_PRIM_IB_RESET_INDX[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX[0]), 0, 0 },
{ "mmCB_BLEND_RED", REG_MMIO, 0x0105, 1, &mmCB_BLEND_RED[0], sizeof(mmCB_BLEND_RED)/sizeof(mmCB_BLEND_RED[0]), 0, 0 },
{ "mmCB_BLEND_GREEN", REG_MMIO, 0x0106, 1, &mmCB_BLEND_GREEN[0], sizeof(mmCB_BLEND_GREEN)/sizeof(mmCB_BLEND_GREEN[0]), 0, 0 },
@@ -1973,7 +1969,6 @@
{ "mmVGT_EVENT_INITIATOR", REG_MMIO, 0x02a4, 1, &mmVGT_EVENT_INITIATOR[0], sizeof(mmVGT_EVENT_INITIATOR)/sizeof(mmVGT_EVENT_INITIATOR[0]), 0, 0 },
{ "mmVGT_GS_MAX_PRIMS_PER_SUBGROUP", REG_MMIO, 0x02a5, 1, &mmVGT_GS_MAX_PRIMS_PER_SUBGROUP[0], sizeof(mmVGT_GS_MAX_PRIMS_PER_SUBGROUP)/sizeof(mmVGT_GS_MAX_PRIMS_PER_SUBGROUP[0]), 0, 0 },
{ "mmVGT_DRAW_PAYLOAD_CNTL", REG_MMIO, 0x02a6, 1, &mmVGT_DRAW_PAYLOAD_CNTL[0], sizeof(mmVGT_DRAW_PAYLOAD_CNTL)/sizeof(mmVGT_DRAW_PAYLOAD_CNTL[0]), 0, 0 },
- { "mmVGT_INDEX_PAYLOAD_CNTL", REG_MMIO, 0x02a7, 1, &mmVGT_INDEX_PAYLOAD_CNTL[0], sizeof(mmVGT_INDEX_PAYLOAD_CNTL)/sizeof(mmVGT_INDEX_PAYLOAD_CNTL[0]), 0, 0 },
{ "mmVGT_INSTANCE_STEP_RATE_0", REG_MMIO, 0x02a8, 1, &mmVGT_INSTANCE_STEP_RATE_0[0], sizeof(mmVGT_INSTANCE_STEP_RATE_0)/sizeof(mmVGT_INSTANCE_STEP_RATE_0[0]), 0, 0 },
{ "mmVGT_INSTANCE_STEP_RATE_1", REG_MMIO, 0x02a9, 1, &mmVGT_INSTANCE_STEP_RATE_1[0], sizeof(mmVGT_INSTANCE_STEP_RATE_1)/sizeof(mmVGT_INSTANCE_STEP_RATE_1[0]), 0, 0 },
{ "mmVGT_ESGS_RING_ITEMSIZE", REG_MMIO, 0x02ab, 1, &mmVGT_ESGS_RING_ITEMSIZE[0], sizeof(mmVGT_ESGS_RING_ITEMSIZE)/sizeof(mmVGT_ESGS_RING_ITEMSIZE[0]), 0, 0 },
@@ -2388,7 +2383,6 @@
{ "mmWD_INDEX_BUF_BASE", REG_MMIO, 0x2256, 1, &mmWD_INDEX_BUF_BASE[0], sizeof(mmWD_INDEX_BUF_BASE)/sizeof(mmWD_INDEX_BUF_BASE[0]), 0, 0 },
{ "mmWD_INDEX_BUF_BASE_HI", REG_MMIO, 0x2257, 1, &mmWD_INDEX_BUF_BASE_HI[0], sizeof(mmWD_INDEX_BUF_BASE_HI)/sizeof(mmWD_INDEX_BUF_BASE_HI[0]), 0, 0 },
{ "mmIA_MULTI_VGT_PARAM", REG_MMIO, 0x2258, 1, &mmIA_MULTI_VGT_PARAM[0], sizeof(mmIA_MULTI_VGT_PARAM)/sizeof(mmIA_MULTI_VGT_PARAM[0]), 0, 0 },
- { "mmVGT_OBJECT_ID", REG_MMIO, 0x2259, 1, &mmVGT_OBJECT_ID[0], sizeof(mmVGT_OBJECT_ID)/sizeof(mmVGT_OBJECT_ID[0]), 0, 0 },
{ "mmVGT_INSTANCE_BASE_ID", REG_MMIO, 0x225a, 1, &mmVGT_INSTANCE_BASE_ID[0], sizeof(mmVGT_INSTANCE_BASE_ID)/sizeof(mmVGT_INSTANCE_BASE_ID[0]), 0, 0 },
{ "mmPA_SU_LINE_STIPPLE_VALUE", REG_MMIO, 0x2280, 1, &mmPA_SU_LINE_STIPPLE_VALUE[0], sizeof(mmPA_SU_LINE_STIPPLE_VALUE)/sizeof(mmPA_SU_LINE_STIPPLE_VALUE[0]), 0, 0 },
{ "mmPA_SC_LINE_STIPPLE_STATE", REG_MMIO, 0x2281, 1, &mmPA_SC_LINE_STIPPLE_STATE[0], sizeof(mmPA_SC_LINE_STIPPLE_STATE)/sizeof(mmPA_SC_LINE_STIPPLE_STATE[0]), 0, 0 },
@@ -2432,7 +2426,6 @@
{ "mmSQC_WRITEBACK", REG_MMIO, 0x2349, 1, &mmSQC_WRITEBACK[0], sizeof(mmSQC_WRITEBACK)/sizeof(mmSQC_WRITEBACK[0]), 0, 0 },
{ "mmTA_CS_BC_BASE_ADDR", REG_MMIO, 0x2380, 1, &mmTA_CS_BC_BASE_ADDR[0], sizeof(mmTA_CS_BC_BASE_ADDR)/sizeof(mmTA_CS_BC_BASE_ADDR[0]), 0, 0 },
{ "mmTA_CS_BC_BASE_ADDR_HI", REG_MMIO, 0x2381, 1, &mmTA_CS_BC_BASE_ADDR_HI[0], sizeof(mmTA_CS_BC_BASE_ADDR_HI)/sizeof(mmTA_CS_BC_BASE_ADDR_HI[0]), 0, 0 },
- { "mmTA_GRAD_ADJ_UCONFIG", REG_MMIO, 0x2382, 1, &mmTA_GRAD_ADJ_UCONFIG[0], sizeof(mmTA_GRAD_ADJ_UCONFIG)/sizeof(mmTA_GRAD_ADJ_UCONFIG[0]), 0, 0 },
{ "mmDB_OCCLUSION_COUNT0_LOW", REG_MMIO, 0x23c0, 1, &mmDB_OCCLUSION_COUNT0_LOW[0], sizeof(mmDB_OCCLUSION_COUNT0_LOW)/sizeof(mmDB_OCCLUSION_COUNT0_LOW[0]), 0, 0 },
{ "mmDB_OCCLUSION_COUNT0_HI", REG_MMIO, 0x23c1, 1, &mmDB_OCCLUSION_COUNT0_HI[0], sizeof(mmDB_OCCLUSION_COUNT0_HI)/sizeof(mmDB_OCCLUSION_COUNT0_HI[0]), 0, 0 },
{ "mmDB_OCCLUSION_COUNT1_LOW", REG_MMIO, 0x23c2, 1, &mmDB_OCCLUSION_COUNT1_LOW[0], sizeof(mmDB_OCCLUSION_COUNT1_LOW)/sizeof(mmDB_OCCLUSION_COUNT1_LOW[0]), 0, 0 },
diff --git a/src/lib/ip/hdp40_bits.i b/src/lib/ip/hdp40_bits.i
index 240983f6e01a..53449c01f1cc 100644
--- a/src/lib/ip/hdp40_bits.i
+++ b/src/lib/ip/hdp40_bits.i
@@ -1,422 +1,180 @@
static struct umr_bitfield mmHDP_MMHUB_TLVL[] = {
- { "HDP_WR_TLVL", 0, 2, &umr_bitfield_default },
- { "HDP_RD_TLVL", 4, 6, &umr_bitfield_default },
- { "XDP_WR_TLVL", 8, 10, &umr_bitfield_default },
- { "XDP_RD_TLVL", 12, 14, &umr_bitfield_default },
- { "XDP_MBX_WR_TLVL", 16, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MMHUB_UNITID[] = {
- { "HDP_UNITID", 0, 5, &umr_bitfield_default },
- { "XDP_UNITID", 8, 13, &umr_bitfield_default },
- { "XDP_MBX_UNITID", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURFACE_BASE[] = {
- { "NONSURF_BASE_39_8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURFACE_INFO[] = {
- { "NONSURF_SWAP", 4, 5, &umr_bitfield_default },
- { "NONSURF_VMID", 8, 11, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURFACE_BASE_HI[] = {
- { "NONSURF_BASE_47_40", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURF_FLAGS[] = {
- { "NONSURF_WRITE_FLAG", 0, 0, &umr_bitfield_default },
- { "NONSURF_READ_FLAG", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_NONSURF_FLAGS_CLR[] = {
- { "NONSURF_WRITE_FLAG_CLR", 0, 0, &umr_bitfield_default },
- { "NONSURF_READ_FLAG_CLR", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_HOST_PATH_CNTL[] = {
- { "WR_STALL_TIMER", 9, 10, &umr_bitfield_default },
- { "RD_STALL_TIMER", 11, 12, &umr_bitfield_default },
- { "WRITE_COMBINE_TIMER_PRELOAD_CFG", 18, 18, &umr_bitfield_default },
- { "WRITE_COMBINE_TIMER", 19, 20, &umr_bitfield_default },
- { "WRITE_COMBINE_EN", 21, 21, &umr_bitfield_default },
- { "WRITE_COMBINE_64B_EN", 22, 22, &umr_bitfield_default },
- { "ALL_SURFACES_DIS", 29, 29, &umr_bitfield_default },
- { "WRITE_THROUGH_CACHE_DIS", 30, 30, &umr_bitfield_default },
- { "LIN_RD_CACHE_DIS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_SW_SEMAPHORE[] = {
- { "SW_SEMAPHORE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_DEBUG0[] = {
- { "HDP_DEBUG", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_LAST_SURFACE_HIT[] = {
- { "LAST_SURFACE_HIT", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_READ_CACHE_INVALIDATE[] = {
- { "READ_CACHE_INVALIDATE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_OUTSTANDING_REQ[] = {
- { "WRITE_REQ", 0, 7, &umr_bitfield_default },
- { "READ_REQ", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MISC_CNTL[] = {
- { "FLUSH_INVALIDATE_CACHE", 0, 0, &umr_bitfield_default },
- { "IDLE_HYSTERESIS_CNTL", 2, 3, &umr_bitfield_default },
- { "OUTSTANDING_WRITE_COUNT_1024", 5, 5, &umr_bitfield_default },
- { "MULTIPLE_READS", 6, 6, &umr_bitfield_default },
- { "SIMULTANEOUS_READS_WRITES", 11, 11, &umr_bitfield_default },
- { "FED_ENABLE", 21, 21, &umr_bitfield_default },
- { "SYSHUB_CHANNEL_PRIORITY", 23, 23, &umr_bitfield_default },
- { "MMHUB_WRBURST_ENABLE", 24, 24, &umr_bitfield_default },
- { "ALL_FUNCTION_CACHELINE_INVALID", 25, 25, &umr_bitfield_default },
- { "HDP_MMHUB_PENDING_WR_TAG_CHECK", 26, 26, &umr_bitfield_default },
- { "XDP_MMHUB_PENDING_WR_TAG_CHECK", 27, 27, &umr_bitfield_default },
- { "VARIABLE_CACHELINE_SIZE", 28, 28, &umr_bitfield_default },
- { "ADAPTIVE_CACHELINE_SIZE", 29, 29, &umr_bitfield_default },
- { "MMHUB_WRBURST_SIZE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEM_POWER_LS[] = {
- { "LS_ENABLE", 0, 0, &umr_bitfield_default },
- { "LS_HOLD", 7, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MMHUB_CNTL[] = {
- { "HDP_MMHUB_RO", 0, 0, &umr_bitfield_default },
- { "HDP_MMHUB_GCC", 1, 1, &umr_bitfield_default },
- { "HDP_MMHUB_SNOOP", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_EDC_CNT[] = {
- { "MEM0_SED_COUNT", 0, 1, &umr_bitfield_default },
- { "MEM1_SED_COUNT", 2, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_VERSION[] = {
- { "MINVER", 0, 7, &umr_bitfield_default },
- { "MAJVER", 8, 15, &umr_bitfield_default },
- { "REV", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_CLK_CNTL[] = {
- { "REG_CLK_ENABLE_COUNT", 0, 3, &umr_bitfield_default },
- { "REG_WAKE_DYN_CLK", 4, 4, &umr_bitfield_default },
- { "DBUS_CLK_SOFT_OVERRIDE", 28, 28, &umr_bitfield_default },
- { "DYN_CLK_SOFT_OVERRIDE", 29, 29, &umr_bitfield_default },
- { "XDP_REG_CLK_SOFT_OVERRIDE", 30, 30, &umr_bitfield_default },
- { "HDP_REG_CLK_SOFT_OVERRIDE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEMIO_CNTL[] = {
- { "MEMIO_SEND", 0, 0, &umr_bitfield_default },
- { "MEMIO_OP", 1, 1, &umr_bitfield_default },
- { "MEMIO_BE", 2, 5, &umr_bitfield_default },
- { "MEMIO_WR_STROBE", 6, 6, &umr_bitfield_default },
- { "MEMIO_RD_STROBE", 7, 7, &umr_bitfield_default },
- { "MEMIO_ADDR_UPPER", 8, 13, &umr_bitfield_default },
- { "MEMIO_CLR_WR_ERROR", 14, 14, &umr_bitfield_default },
- { "MEMIO_CLR_RD_ERROR", 15, 15, &umr_bitfield_default },
- { "MEMIO_VF", 16, 16, &umr_bitfield_default },
- { "MEMIO_VFID", 17, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEMIO_ADDR[] = {
- { "MEMIO_ADDR_LOWER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEMIO_STATUS[] = {
- { "MEMIO_WR_STATUS", 0, 0, &umr_bitfield_default },
- { "MEMIO_RD_STATUS", 1, 1, &umr_bitfield_default },
- { "MEMIO_WR_ERROR", 2, 2, &umr_bitfield_default },
- { "MEMIO_RD_ERROR", 3, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEMIO_WR_DATA[] = {
- { "MEMIO_WR_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_MEMIO_RD_DATA[] = {
- { "MEMIO_RD_DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_DIRECT2HDP_FIRST[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_FLUSH[] = {
- { "D2H_FLUSH_FLUSH_NUM", 0, 3, &umr_bitfield_default },
- { "D2H_FLUSH_MBX_ENC_DATA", 4, 7, &umr_bitfield_default },
- { "D2H_FLUSH_MBX_ADDR_SEL", 8, 10, &umr_bitfield_default },
- { "D2H_FLUSH_XPB_CLG", 11, 15, &umr_bitfield_default },
- { "D2H_FLUSH_SEND_HOST", 16, 16, &umr_bitfield_default },
- { "D2H_FLUSH_ALTER_FLUSH_NUM", 18, 18, &umr_bitfield_default },
- { "D2H_FLUSH_RSVD_0", 19, 19, &umr_bitfield_default },
- { "D2H_FLUSH_RSVD_1", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_BAR_UPDATE[] = {
- { "D2H_BAR_UPDATE_ADDR", 0, 15, &umr_bitfield_default },
- { "D2H_BAR_UPDATE_FLUSH_NUM", 16, 19, &umr_bitfield_default },
- { "D2H_BAR_UPDATE_BAR_NUM", 20, 22, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_3[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_4[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_5[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_6[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_7[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_8[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_9[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_10[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_11[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_12[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_13[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_14[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_15[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_16[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_17[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_18[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_19[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_20[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_21[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_22[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_23[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_24[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_25[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_26[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_27[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_28[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_29[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_30[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_31[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_32[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_33[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_D2H_RSVD_34[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_DIRECT2HDP_LAST[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR_CFG[] = {
- { "P2P_BAR_CFG_ADDR_SIZE", 0, 3, &umr_bitfield_default },
- { "P2P_BAR_CFG_BAR_FROM", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_OFFSET[] = {
- { "P2P_MBX_OFFSET", 0, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR0[] = {
- { "VALID", 0, 0, &umr_bitfield_default },
- { "ADDR_35_19", 3, 19, &umr_bitfield_default },
- { "ADDR_39_36", 20, 23, &umr_bitfield_default },
- { "ADDR_47_40", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR1[] = {
- { "VALID", 0, 0, &umr_bitfield_default },
- { "ADDR_35_19", 3, 19, &umr_bitfield_default },
- { "ADDR_39_36", 20, 23, &umr_bitfield_default },
- { "ADDR_47_40", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR2[] = {
- { "VALID", 0, 0, &umr_bitfield_default },
- { "ADDR_35_19", 3, 19, &umr_bitfield_default },
- { "ADDR_39_36", 20, 23, &umr_bitfield_default },
- { "ADDR_47_40", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR3[] = {
- { "VALID", 0, 0, &umr_bitfield_default },
- { "ADDR_35_19", 3, 19, &umr_bitfield_default },
- { "ADDR_39_36", 20, 23, &umr_bitfield_default },
- { "ADDR_47_40", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR4[] = {
- { "VALID", 0, 0, &umr_bitfield_default },
- { "ADDR_35_19", 3, 19, &umr_bitfield_default },
- { "ADDR_39_36", 20, 23, &umr_bitfield_default },
- { "ADDR_47_40", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR5[] = {
- { "VALID", 0, 0, &umr_bitfield_default },
- { "ADDR_35_19", 3, 19, &umr_bitfield_default },
- { "ADDR_39_36", 20, 23, &umr_bitfield_default },
- { "ADDR_47_40", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR6[] = {
- { "VALID", 0, 0, &umr_bitfield_default },
- { "ADDR_35_19", 3, 19, &umr_bitfield_default },
- { "ADDR_39_36", 20, 23, &umr_bitfield_default },
- { "ADDR_47_40", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_HDP_MBX_MC_CFG[] = {
- { "HDP_MBX_MC_CFG_TAP_WRREQ_QOS", 0, 3, &umr_bitfield_default },
- { "HDP_MBX_MC_CFG_TAP_WRREQ_SWAP", 4, 5, &umr_bitfield_default },
- { "HDP_MBX_MC_CFG_TAP_WRREQ_VMID", 8, 11, &umr_bitfield_default },
- { "HDP_MBX_MC_CFG_TAP_WRREQ_RO", 12, 12, &umr_bitfield_default },
- { "HDP_MBX_MC_CFG_TAP_WRREQ_GCC", 13, 13, &umr_bitfield_default },
- { "HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP", 14, 14, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_HDP_MC_CFG[] = {
- { "HDP_MC_CFG_HST_TAP_REQ_SNOOP", 3, 3, &umr_bitfield_default },
- { "HDP_MC_CFG_HST_TAP_REQ_SWAP", 4, 5, &umr_bitfield_default },
- { "HDP_MC_CFG_HST_TAP_REQ_VMID", 8, 11, &umr_bitfield_default },
- { "HDP_MC_CFG_HST_TAP_REQ_RO", 12, 12, &umr_bitfield_default },
- { "HDP_MC_CFG_HST_TAP_REQ_GCC", 13, 13, &umr_bitfield_default },
- { "HDP_MC_CFG_XDP_HIGHER_PRI_THRESH", 14, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_HST_CFG[] = {
- { "HST_CFG_WR_COMBINE_EN", 0, 0, &umr_bitfield_default },
- { "HST_CFG_WR_COMBINE_TIMER", 1, 2, &umr_bitfield_default },
- { "HST_CFG_WR_BURST_EN", 3, 3, &umr_bitfield_default },
- { "HST_CFG_WR_COMBINE_64B_EN", 4, 4, &umr_bitfield_default },
- { "HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG", 5, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_HDP_IPH_CFG[] = {
- { "HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE", 0, 5, &umr_bitfield_default },
- { "HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE", 6, 11, &umr_bitfield_default },
- { "HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING", 12, 12, &umr_bitfield_default },
- { "HDP_IPH_CFG_P2P_RD_EN", 13, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR0[] = {
- { "ADDR", 0, 15, &umr_bitfield_default },
- { "FLUSH", 16, 19, &umr_bitfield_default },
- { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR1[] = {
- { "ADDR", 0, 15, &umr_bitfield_default },
- { "FLUSH", 16, 19, &umr_bitfield_default },
- { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR2[] = {
- { "ADDR", 0, 15, &umr_bitfield_default },
- { "FLUSH", 16, 19, &umr_bitfield_default },
- { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR3[] = {
- { "ADDR", 0, 15, &umr_bitfield_default },
- { "FLUSH", 16, 19, &umr_bitfield_default },
- { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR4[] = {
- { "ADDR", 0, 15, &umr_bitfield_default },
- { "FLUSH", 16, 19, &umr_bitfield_default },
- { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR5[] = {
- { "ADDR", 0, 15, &umr_bitfield_default },
- { "FLUSH", 16, 19, &umr_bitfield_default },
- { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR6[] = {
- { "ADDR", 0, 15, &umr_bitfield_default },
- { "FLUSH", 16, 19, &umr_bitfield_default },
- { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_P2P_BAR7[] = {
- { "ADDR", 0, 15, &umr_bitfield_default },
- { "FLUSH", 16, 19, &umr_bitfield_default },
- { "VALID", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_FLUSH_ARMED_STS[] = {
- { "FLUSH_ARMED_STS", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_FLUSH_CNTR0_STS[] = {
- { "FLUSH_CNTR0_STS", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_BUSY_STS[] = {
- { "BUSY_BITS", 0, 17, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_STICKY[] = {
- { "STICKY_STS", 0, 15, &umr_bitfield_default },
- { "STICKY_W1C", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_CHKN[] = {
- { "CHKN_0_RSVD", 0, 7, &umr_bitfield_default },
- { "CHKN_1_RSVD", 8, 15, &umr_bitfield_default },
- { "CHKN_2_RSVD", 16, 23, &umr_bitfield_default },
- { "CHKN_3_RSVD", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_BARS_ADDR_39_36[] = {
- { "BAR0_ADDR_39_36", 0, 3, &umr_bitfield_default },
- { "BAR1_ADDR_39_36", 4, 7, &umr_bitfield_default },
- { "BAR2_ADDR_39_36", 8, 11, &umr_bitfield_default },
- { "BAR3_ADDR_39_36", 12, 15, &umr_bitfield_default },
- { "BAR4_ADDR_39_36", 16, 19, &umr_bitfield_default },
- { "BAR5_ADDR_39_36", 20, 23, &umr_bitfield_default },
- { "BAR6_ADDR_39_36", 24, 27, &umr_bitfield_default },
- { "BAR7_ADDR_39_36", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_MC_VM_FB_LOCATION_BASE[] = {
- { "FB_BASE", 0, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_GPU_IOV_VIOLATION_LOG[] = {
- { "VIOLATION_STATUS", 0, 0, &umr_bitfield_default },
- { "MULTIPLE_VIOLATION_STATUS", 1, 1, &umr_bitfield_default },
- { "ADDRESS", 2, 17, &umr_bitfield_default },
- { "OPCODE", 18, 18, &umr_bitfield_default },
- { "VF", 19, 19, &umr_bitfield_default },
- { "VFID", 20, 23, &umr_bitfield_default },
- { "INITIATOR_ID", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmHDP_XDP_MMHUB_ERROR[] = {
- { "HDP_BRESP_01", 1, 1, &umr_bitfield_default },
- { "HDP_BRESP_10", 2, 2, &umr_bitfield_default },
- { "HDP_BRESP_11", 3, 3, &umr_bitfield_default },
- { "HDP_BUSER_NACK_01", 5, 5, &umr_bitfield_default },
- { "HDP_BUSER_NACK_10", 6, 6, &umr_bitfield_default },
- { "HDP_BUSER_NACK_11", 7, 7, &umr_bitfield_default },
- { "HDP_RRESP_01", 9, 9, &umr_bitfield_default },
- { "HDP_RRESP_10", 10, 10, &umr_bitfield_default },
- { "HDP_RRESP_11", 11, 11, &umr_bitfield_default },
- { "HDP_RUSER_NACK_01", 13, 13, &umr_bitfield_default },
- { "HDP_RUSER_NACK_10", 14, 14, &umr_bitfield_default },
- { "HDP_RUSER_NACK_11", 15, 15, &umr_bitfield_default },
- { "XDP_BRESP_01", 17, 17, &umr_bitfield_default },
- { "XDP_BRESP_10", 18, 18, &umr_bitfield_default },
- { "XDP_BRESP_11", 19, 19, &umr_bitfield_default },
- { "XDP_BUSER_NACK_01", 21, 21, &umr_bitfield_default },
- { "XDP_BUSER_NACK_10", 22, 22, &umr_bitfield_default },
- { "XDP_BUSER_NACK_11", 23, 23, &umr_bitfield_default },
};
diff --git a/src/lib/ip/mp90_bits.i b/src/lib/ip/mp90_bits.i
index 002533399403..fea4d4b8d377 100644
--- a/src/lib/ip/mp90_bits.i
+++ b/src/lib/ip/mp90_bits.i
@@ -1,512 +1,336 @@
static struct umr_bitfield mmMP0_SMN_C2PMSG_32[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_33[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_34[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_35[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_36[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_37[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_38[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_39[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_40[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_41[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_42[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_43[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_44[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_45[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_46[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_47[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_48[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_49[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_50[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_51[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_52[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_53[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_54[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_55[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_56[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_57[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_58[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_59[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_60[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_61[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_62[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_63[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_64[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_65[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_66[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_67[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_68[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_69[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_70[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_71[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_72[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_73[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_74[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_75[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_76[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_77[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_78[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_79[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_80[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_81[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_82[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_83[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_84[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_85[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_86[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_87[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_88[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_89[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_90[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_91[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_92[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_93[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_94[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_95[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_96[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_97[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_98[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_99[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_100[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_101[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_102[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_C2PMSG_103[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_ACTIVE_FCN_ID[] = {
- { "VFID", 0, 3, &umr_bitfield_default },
- { "VF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_IH_CREDIT[] = {
- { "CREDIT_VALUE", 0, 1, &umr_bitfield_default },
- { "CLIENT_ID", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_IH_SW_INT[] = {
- { "VALID", 0, 0, &umr_bitfield_default },
- { "ID", 1, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMP0_SMN_IH_SW_INT_CTRL[] = {
- { "SW_TRIG_MASK", 0, 0, &umr_bitfield_default },
- { "SW_INT_ACK", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_ACP2MP_RESP[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_DC2MP_RESP[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_UVD2MP_RESP[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_VCE2MP_RESP[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_RLC2MP_RESP[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_32[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_33[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_34[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_35[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_36[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_37[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_38[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_39[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_40[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_41[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_42[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_43[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_44[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_45[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_46[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_47[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_48[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_49[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_50[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_51[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_52[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_53[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_54[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_55[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_56[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_57[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_58[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_59[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_60[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_61[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_62[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_63[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_64[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_65[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_66[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_67[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_68[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_69[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_70[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_71[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_72[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_73[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_74[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_75[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_76[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_77[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_78[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_79[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_80[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_81[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_82[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_83[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_84[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_85[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_86[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_87[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_88[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_89[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_90[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_91[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_92[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_93[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_94[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_95[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_96[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_97[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_98[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_99[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_100[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_101[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_102[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_C2PMSG_103[] = {
- { "CONTENT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_ACTIVE_FCN_ID[] = {
- { "VFID", 0, 3, &umr_bitfield_default },
- { "VF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_IH_CREDIT[] = {
- { "CREDIT_VALUE", 0, 1, &umr_bitfield_default },
- { "CLIENT_ID", 16, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_IH_SW_INT[] = {
- { "VALID", 0, 0, &umr_bitfield_default },
- { "ID", 1, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_IH_SW_INT_CTRL[] = {
- { "SW_TRIG_MASK", 0, 0, &umr_bitfield_default },
- { "SW_INT_ACK", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_FPS_CNT[] = {
- { "COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_EXT_SCRATCH0[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_EXT_SCRATCH1[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_EXT_SCRATCH2[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_EXT_SCRATCH3[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_EXT_SCRATCH4[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_EXT_SCRATCH5[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_EXT_SCRATCH6[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_EXT_SCRATCH7[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_EXT_SCRATCH8[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmMP1_SMN_PUB_CTRL[] = {
- { "RESET", 0, 0, &umr_bitfield_default },
};
diff --git a/src/lib/ip/sdma040_bits.i b/src/lib/ip/sdma040_bits.i
index b2cfe3a0d426..4a13ef4c883e 100644
--- a/src/lib/ip/sdma040_bits.i
+++ b/src/lib/ip/sdma040_bits.i
@@ -1,1301 +1,518 @@
static struct umr_bitfield mmSDMA0_UCODE_ADDR[] = {
- { "VALUE", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UCODE_DATA[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_VM_CNTL[] = {
- { "CMD", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_VM_CTX_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_VM_CTX_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_ACTIVE_FCN_ID[] = {
- { "VFID", 0, 3, &umr_bitfield_default },
- { "RESERVED", 4, 30, &umr_bitfield_default },
- { "VF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_VM_CTX_CNTL[] = {
- { "PRIV", 0, 0, &umr_bitfield_default },
- { "VMID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_VIRT_RESET_REQ[] = {
- { "VF", 0, 15, &umr_bitfield_default },
- { "PF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_VF_ENABLE[] = {
- { "VF_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE0[] = {
- { "SDMA0_GFX_RB_CNTL", 0, 0, &umr_bitfield_default },
- { "SDMA0_GFX_RB_BASE", 1, 1, &umr_bitfield_default },
- { "SDMA0_GFX_RB_BASE_HI", 2, 2, &umr_bitfield_default },
- { "SDMA0_GFX_RB_RPTR", 3, 3, &umr_bitfield_default },
- { "SDMA0_GFX_RB_RPTR_HI", 4, 4, &umr_bitfield_default },
- { "SDMA0_GFX_RB_WPTR", 5, 5, &umr_bitfield_default },
- { "SDMA0_GFX_RB_WPTR_HI", 6, 6, &umr_bitfield_default },
- { "SDMA0_GFX_RB_WPTR_POLL_CNTL", 7, 7, &umr_bitfield_default },
- { "SDMA0_GFX_RB_RPTR_ADDR_HI", 8, 8, &umr_bitfield_default },
- { "SDMA0_GFX_RB_RPTR_ADDR_LO", 9, 9, &umr_bitfield_default },
- { "SDMA0_GFX_IB_CNTL", 10, 10, &umr_bitfield_default },
- { "SDMA0_GFX_IB_RPTR", 11, 11, &umr_bitfield_default },
- { "SDMA0_GFX_IB_OFFSET", 12, 12, &umr_bitfield_default },
- { "SDMA0_GFX_IB_BASE_LO", 13, 13, &umr_bitfield_default },
- { "SDMA0_GFX_IB_BASE_HI", 14, 14, &umr_bitfield_default },
- { "SDMA0_GFX_IB_SIZE", 15, 15, &umr_bitfield_default },
- { "SDMA0_GFX_SKIP_CNTL", 16, 16, &umr_bitfield_default },
- { "SDMA0_GFX_CONTEXT_STATUS", 17, 17, &umr_bitfield_default },
- { "SDMA0_GFX_DOORBELL", 18, 18, &umr_bitfield_default },
- { "SDMA0_GFX_CONTEXT_CNTL", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE1[] = {
- { "SDMA0_GFX_STATUS", 8, 8, &umr_bitfield_default },
- { "SDMA0_GFX_DOORBELL_LOG", 9, 9, &umr_bitfield_default },
- { "SDMA0_GFX_WATERMARK", 10, 10, &umr_bitfield_default },
- { "SDMA0_GFX_DOORBELL_OFFSET", 11, 11, &umr_bitfield_default },
- { "SDMA0_GFX_CSA_ADDR_LO", 12, 12, &umr_bitfield_default },
- { "SDMA0_GFX_CSA_ADDR_HI", 13, 13, &umr_bitfield_default },
- { "VOID_REG2", 14, 14, &umr_bitfield_default },
- { "SDMA0_GFX_IB_SUB_REMAIN", 15, 15, &umr_bitfield_default },
- { "SDMA0_GFX_PREEMPT", 16, 16, &umr_bitfield_default },
- { "SDMA0_GFX_DUMMY_REG", 17, 17, &umr_bitfield_default },
- { "SDMA0_GFX_RB_WPTR_POLL_ADDR_HI", 18, 18, &umr_bitfield_default },
- { "SDMA0_GFX_RB_WPTR_POLL_ADDR_LO", 19, 19, &umr_bitfield_default },
- { "SDMA0_GFX_RB_AQL_CNTL", 20, 20, &umr_bitfield_default },
- { "SDMA0_GFX_MINOR_PTR_UPDATE", 21, 21, &umr_bitfield_default },
- { "RESERVED", 22, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE2[] = {
- { "SDMA0_GFX_MIDCMD_DATA0", 0, 0, &umr_bitfield_default },
- { "SDMA0_GFX_MIDCMD_DATA1", 1, 1, &umr_bitfield_default },
- { "SDMA0_GFX_MIDCMD_DATA2", 2, 2, &umr_bitfield_default },
- { "SDMA0_GFX_MIDCMD_DATA3", 3, 3, &umr_bitfield_default },
- { "SDMA0_GFX_MIDCMD_DATA4", 4, 4, &umr_bitfield_default },
- { "SDMA0_GFX_MIDCMD_DATA5", 5, 5, &umr_bitfield_default },
- { "SDMA0_GFX_MIDCMD_DATA6", 6, 6, &umr_bitfield_default },
- { "SDMA0_GFX_MIDCMD_DATA7", 7, 7, &umr_bitfield_default },
- { "SDMA0_GFX_MIDCMD_DATA8", 8, 8, &umr_bitfield_default },
- { "SDMA0_GFX_MIDCMD_CNTL", 9, 9, &umr_bitfield_default },
- { "RESERVED", 10, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE3[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PUB_REG_TYPE0[] = {
- { "SDMA0_UCODE_ADDR", 0, 0, &umr_bitfield_default },
- { "SDMA0_UCODE_DATA", 1, 1, &umr_bitfield_default },
- { "RESERVED3", 3, 3, &umr_bitfield_default },
- { "SDMA0_VM_CNTL", 4, 4, &umr_bitfield_default },
- { "SDMA0_VM_CTX_LO", 5, 5, &umr_bitfield_default },
- { "SDMA0_VM_CTX_HI", 6, 6, &umr_bitfield_default },
- { "SDMA0_ACTIVE_FCN_ID", 7, 7, &umr_bitfield_default },
- { "SDMA0_VM_CTX_CNTL", 8, 8, &umr_bitfield_default },
- { "SDMA0_VIRT_RESET_REQ", 9, 9, &umr_bitfield_default },
- { "RESERVED10", 10, 10, &umr_bitfield_default },
- { "SDMA0_CONTEXT_REG_TYPE0", 11, 11, &umr_bitfield_default },
- { "SDMA0_CONTEXT_REG_TYPE1", 12, 12, &umr_bitfield_default },
- { "SDMA0_CONTEXT_REG_TYPE2", 13, 13, &umr_bitfield_default },
- { "SDMA0_CONTEXT_REG_TYPE3", 14, 14, &umr_bitfield_default },
- { "SDMA0_PUB_REG_TYPE0", 15, 15, &umr_bitfield_default },
- { "SDMA0_PUB_REG_TYPE1", 16, 16, &umr_bitfield_default },
- { "SDMA0_PUB_REG_TYPE2", 17, 17, &umr_bitfield_default },
- { "SDMA0_PUB_REG_TYPE3", 18, 18, &umr_bitfield_default },
- { "SDMA0_MMHUB_CNTL", 19, 19, &umr_bitfield_default },
- { "RESERVED_FOR_PSPSMU_ACCESS_ONLY", 20, 24, &umr_bitfield_default },
- { "SDMA0_CONTEXT_GROUP_BOUNDARY", 25, 25, &umr_bitfield_default },
- { "SDMA0_POWER_CNTL", 26, 26, &umr_bitfield_default },
- { "SDMA0_CLK_CTRL", 27, 27, &umr_bitfield_default },
- { "SDMA0_CNTL", 28, 28, &umr_bitfield_default },
- { "SDMA0_CHICKEN_BITS", 29, 29, &umr_bitfield_default },
- { "SDMA0_GB_ADDR_CONFIG", 30, 30, &umr_bitfield_default },
- { "SDMA0_GB_ADDR_CONFIG_READ", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PUB_REG_TYPE1[] = {
- { "SDMA0_RB_RPTR_FETCH_HI", 0, 0, &umr_bitfield_default },
- { "SDMA0_SEM_WAIT_FAIL_TIMER_CNTL", 1, 1, &umr_bitfield_default },
- { "SDMA0_RB_RPTR_FETCH", 2, 2, &umr_bitfield_default },
- { "SDMA0_IB_OFFSET_FETCH", 3, 3, &umr_bitfield_default },
- { "SDMA0_PROGRAM", 4, 4, &umr_bitfield_default },
- { "SDMA0_STATUS_REG", 5, 5, &umr_bitfield_default },
- { "SDMA0_STATUS1_REG", 6, 6, &umr_bitfield_default },
- { "SDMA0_RD_BURST_CNTL", 7, 7, &umr_bitfield_default },
- { "SDMA0_HBM_PAGE_CONFIG", 8, 8, &umr_bitfield_default },
- { "SDMA0_UCODE_CHECKSUM", 9, 9, &umr_bitfield_default },
- { "SDMA0_F32_CNTL", 10, 10, &umr_bitfield_default },
- { "SDMA0_FREEZE", 11, 11, &umr_bitfield_default },
- { "SDMA0_PHASE0_QUANTUM", 12, 12, &umr_bitfield_default },
- { "SDMA0_PHASE1_QUANTUM", 13, 13, &umr_bitfield_default },
- { "SDMA_POWER_GATING", 14, 14, &umr_bitfield_default },
- { "SDMA_PGFSM_CONFIG", 15, 15, &umr_bitfield_default },
- { "SDMA_PGFSM_WRITE", 16, 16, &umr_bitfield_default },
- { "SDMA_PGFSM_READ", 17, 17, &umr_bitfield_default },
- { "SDMA0_EDC_CONFIG", 18, 18, &umr_bitfield_default },
- { "SDMA0_BA_THRESHOLD", 19, 19, &umr_bitfield_default },
- { "SDMA0_ID", 20, 20, &umr_bitfield_default },
- { "SDMA0_VERSION", 21, 21, &umr_bitfield_default },
- { "SDMA0_EDC_COUNTER", 22, 22, &umr_bitfield_default },
- { "SDMA0_EDC_COUNTER_CLEAR", 23, 23, &umr_bitfield_default },
- { "SDMA0_STATUS2_REG", 24, 24, &umr_bitfield_default },
- { "SDMA0_ATOMIC_CNTL", 25, 25, &umr_bitfield_default },
- { "SDMA0_ATOMIC_PREOP_LO", 26, 26, &umr_bitfield_default },
- { "SDMA0_ATOMIC_PREOP_HI", 27, 27, &umr_bitfield_default },
- { "SDMA0_UTCL1_CNTL", 28, 28, &umr_bitfield_default },
- { "SDMA0_UTCL1_WATERMK", 29, 29, &umr_bitfield_default },
- { "SDMA0_UTCL1_RD_STATUS", 30, 30, &umr_bitfield_default },
- { "SDMA0_UTCL1_WR_STATUS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PUB_REG_TYPE2[] = {
- { "SDMA0_UTCL1_INV0", 0, 0, &umr_bitfield_default },
- { "SDMA0_UTCL1_INV1", 1, 1, &umr_bitfield_default },
- { "SDMA0_UTCL1_INV2", 2, 2, &umr_bitfield_default },
- { "SDMA0_UTCL1_RD_XNACK0", 3, 3, &umr_bitfield_default },
- { "SDMA0_UTCL1_RD_XNACK1", 4, 4, &umr_bitfield_default },
- { "SDMA0_UTCL1_WR_XNACK0", 5, 5, &umr_bitfield_default },
- { "SDMA0_UTCL1_WR_XNACK1", 6, 6, &umr_bitfield_default },
- { "SDMA0_UTCL1_TIMEOUT", 7, 7, &umr_bitfield_default },
- { "SDMA0_UTCL1_PAGE", 8, 8, &umr_bitfield_default },
- { "SDMA0_POWER_CNTL_IDLE", 9, 9, &umr_bitfield_default },
- { "SDMA0_RELAX_ORDERING_LUT", 10, 10, &umr_bitfield_default },
- { "SDMA0_CHICKEN_BITS_2", 11, 11, &umr_bitfield_default },
- { "SDMA0_STATUS3_REG", 12, 12, &umr_bitfield_default },
- { "SDMA0_PHYSICAL_ADDR_LO", 13, 13, &umr_bitfield_default },
- { "SDMA0_PHYSICAL_ADDR_HI", 14, 14, &umr_bitfield_default },
- { "SDMA0_PHASE2_QUANTUM", 15, 15, &umr_bitfield_default },
- { "SDMA0_ERROR_LOG", 16, 16, &umr_bitfield_default },
- { "SDMA0_PUB_DUMMY_REG0", 17, 17, &umr_bitfield_default },
- { "SDMA0_PUB_DUMMY_REG1", 18, 18, &umr_bitfield_default },
- { "SDMA0_PUB_DUMMY_REG2", 19, 19, &umr_bitfield_default },
- { "SDMA0_PUB_DUMMY_REG3", 20, 20, &umr_bitfield_default },
- { "SDMA0_F32_COUNTER", 21, 21, &umr_bitfield_default },
- { "SDMA0_UNBREAKABLE", 22, 22, &umr_bitfield_default },
- { "SDMA0_PERFMON_CNTL", 23, 23, &umr_bitfield_default },
- { "SDMA0_PERFCOUNTER0_RESULT", 24, 24, &umr_bitfield_default },
- { "SDMA0_PERFCOUNTER1_RESULT", 25, 25, &umr_bitfield_default },
- { "SDMA0_PERFCOUNTER_TAG_DELAY_RANGE", 26, 26, &umr_bitfield_default },
- { "SDMA0_CRD_CNTL", 27, 27, &umr_bitfield_default },
- { "SDMA0_MMHUB_TRUSTLVL", 28, 28, &umr_bitfield_default },
- { "SDMA0_GPU_IOV_VIOLATION_LOG", 29, 29, &umr_bitfield_default },
- { "SDMA0_ULV_CNTL", 30, 30, &umr_bitfield_default },
- { "RESERVED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PUB_REG_TYPE3[] = {
- { "SDMA0_EA_DBIT_ADDR_DATA", 0, 0, &umr_bitfield_default },
- { "SDMA0_EA_DBIT_ADDR_INDEX", 1, 1, &umr_bitfield_default },
- { "RESERVED", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_MMHUB_CNTL[] = {
- { "UNIT_ID", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CONTEXT_GROUP_BOUNDARY[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_POWER_CNTL[] = {
- { "PG_CNTL_ENABLE", 0, 0, &umr_bitfield_default },
- { "EXT_PG_POWER_ON_REQ", 1, 1, &umr_bitfield_default },
- { "EXT_PG_POWER_OFF_REQ", 2, 2, &umr_bitfield_default },
- { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default },
- { "MEM_POWER_LS_EN", 9, 9, &umr_bitfield_default },
- { "MEM_POWER_DS_EN", 10, 10, &umr_bitfield_default },
- { "MEM_POWER_SD_EN", 11, 11, &umr_bitfield_default },
- { "MEM_POWER_DELAY", 12, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CLK_CTRL[] = {
- { "ON_DELAY", 0, 3, &umr_bitfield_default },
- { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
- { "RESERVED", 12, 23, &umr_bitfield_default },
- { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
- { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
- { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
- { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
- { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
- { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
- { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
- { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CNTL[] = {
- { "TRAP_ENABLE", 0, 0, &umr_bitfield_default },
- { "UTC_L1_ENABLE", 1, 1, &umr_bitfield_default },
- { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default },
- { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default },
- { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
- { "MIDCMD_PREEMPT_ENABLE", 5, 5, &umr_bitfield_default },
- { "MIDCMD_WORLDSWITCH_ENABLE", 17, 17, &umr_bitfield_default },
- { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default },
- { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default },
- { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default },
- { "IB_PREEMPT_INT_ENABLE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CHICKEN_BITS[] = {
- { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default },
- { "STALL_ON_TRANS_FULL_ENABLE", 1, 1, &umr_bitfield_default },
- { "STALL_ON_NO_FREE_DATA_BUFFER_ENABLE", 2, 2, &umr_bitfield_default },
- { "WRITE_BURST_LENGTH", 8, 9, &umr_bitfield_default },
- { "WRITE_BURST_WAIT_CYCLE", 10, 12, &umr_bitfield_default },
- { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default },
- { "RAW_CHECK_ENABLE", 17, 17, &umr_bitfield_default },
- { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default },
- { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default },
- { "TIME_BASED_QOS", 25, 25, &umr_bitfield_default },
- { "CE_AFIFO_WATERMARK", 26, 27, &umr_bitfield_default },
- { "CE_DFIFO_WATERMARK", 28, 29, &umr_bitfield_default },
- { "CE_LFIFO_WATERMARK", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GB_ADDR_CONFIG[] = {
- { "NUM_PIPES", 0, 2, &umr_bitfield_default },
- { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default },
- { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
- { "NUM_BANKS", 12, 14, &umr_bitfield_default },
- { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GB_ADDR_CONFIG_READ[] = {
- { "NUM_PIPES", 0, 2, &umr_bitfield_default },
- { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default },
- { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
- { "NUM_BANKS", 12, 14, &umr_bitfield_default },
- { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RB_RPTR_FETCH_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[] = {
- { "TIMER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RB_RPTR_FETCH[] = {
- { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_IB_OFFSET_FETCH[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PROGRAM[] = {
- { "STREAM", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_STATUS_REG[] = {
- { "IDLE", 0, 0, &umr_bitfield_default },
- { "REG_IDLE", 1, 1, &umr_bitfield_default },
- { "RB_EMPTY", 2, 2, &umr_bitfield_default },
- { "RB_FULL", 3, 3, &umr_bitfield_default },
- { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default },
- { "RB_CMD_FULL", 5, 5, &umr_bitfield_default },
- { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default },
- { "IB_CMD_FULL", 7, 7, &umr_bitfield_default },
- { "BLOCK_IDLE", 8, 8, &umr_bitfield_default },
- { "INSIDE_IB", 9, 9, &umr_bitfield_default },
- { "EX_IDLE", 10, 10, &umr_bitfield_default },
- { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default },
- { "PACKET_READY", 12, 12, &umr_bitfield_default },
- { "MC_WR_IDLE", 13, 13, &umr_bitfield_default },
- { "SRBM_IDLE", 14, 14, &umr_bitfield_default },
- { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default },
- { "DELTA_RPTR_FULL", 16, 16, &umr_bitfield_default },
- { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default },
- { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default },
- { "MC_RD_IDLE", 19, 19, &umr_bitfield_default },
- { "DELTA_RPTR_EMPTY", 20, 20, &umr_bitfield_default },
- { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default },
- { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default },
- { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default },
- { "SEM_IDLE", 26, 26, &umr_bitfield_default },
- { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default },
- { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default },
- { "INT_IDLE", 30, 30, &umr_bitfield_default },
- { "INT_REQ_STALL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_STATUS1_REG[] = {
- { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default },
- { "CE_WR_IDLE", 1, 1, &umr_bitfield_default },
- { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default },
- { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default },
- { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default },
- { "CE_IN_IDLE", 5, 5, &umr_bitfield_default },
- { "CE_DST_IDLE", 6, 6, &umr_bitfield_default },
- { "CE_CMD_IDLE", 9, 9, &umr_bitfield_default },
- { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default },
- { "CE_INFO_FULL", 13, 13, &umr_bitfield_default },
- { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default },
- { "EX_START", 15, 15, &umr_bitfield_default },
- { "CE_RD_STALL", 17, 17, &umr_bitfield_default },
- { "CE_WR_STALL", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RD_BURST_CNTL[] = {
- { "RD_BURST", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_HBM_PAGE_CONFIG[] = {
- { "PAGE_SIZE_EXPONENT", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UCODE_CHECKSUM[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_F32_CNTL[] = {
- { "HALT", 0, 0, &umr_bitfield_default },
- { "STEP", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_FREEZE[] = {
- { "PREEMPT", 0, 0, &umr_bitfield_default },
- { "FREEZE", 4, 4, &umr_bitfield_default },
- { "FROZEN", 5, 5, &umr_bitfield_default },
- { "F32_FREEZE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PHASE0_QUANTUM[] = {
- { "UNIT", 0, 3, &umr_bitfield_default },
- { "VALUE", 8, 23, &umr_bitfield_default },
- { "PREFER", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PHASE1_QUANTUM[] = {
- { "UNIT", 0, 3, &umr_bitfield_default },
- { "VALUE", 8, 23, &umr_bitfield_default },
- { "PREFER", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA_POWER_GATING[] = {
- { "SDMA0_POWER_OFF_CONDITION", 0, 0, &umr_bitfield_default },
- { "SDMA0_POWER_ON_CONDITION", 1, 1, &umr_bitfield_default },
- { "SDMA0_POWER_OFF_REQ", 2, 2, &umr_bitfield_default },
- { "SDMA0_POWER_ON_REQ", 3, 3, &umr_bitfield_default },
- { "PG_CNTL_STATUS", 4, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA_PGFSM_CONFIG[] = {
- { "FSM_ADDR", 0, 7, &umr_bitfield_default },
- { "POWER_DOWN", 8, 8, &umr_bitfield_default },
- { "POWER_UP", 9, 9, &umr_bitfield_default },
- { "P1_SELECT", 10, 10, &umr_bitfield_default },
- { "P2_SELECT", 11, 11, &umr_bitfield_default },
- { "WRITE", 12, 12, &umr_bitfield_default },
- { "READ", 13, 13, &umr_bitfield_default },
- { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
- { "REG_ADDR", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA_PGFSM_WRITE[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA_PGFSM_READ[] = {
- { "VALUE", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_EDC_CONFIG[] = {
- { "DIS_EDC", 1, 1, &umr_bitfield_default },
- { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_BA_THRESHOLD[] = {
- { "READ_THRES", 0, 9, &umr_bitfield_default },
- { "WRITE_THRES", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_ID[] = {
- { "DEVICE_ID", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_VERSION[] = {
- { "MINVER", 0, 6, &umr_bitfield_default },
- { "MAJVER", 8, 14, &umr_bitfield_default },
- { "REV", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_EDC_COUNTER[] = {
- { "SDMA_UCODE_BUF_DED", 0, 0, &umr_bitfield_default },
- { "SDMA_UCODE_BUF_SEC", 1, 1, &umr_bitfield_default },
- { "SDMA_RB_CMD_BUF_SED", 2, 2, &umr_bitfield_default },
- { "SDMA_IB_CMD_BUF_SED", 3, 3, &umr_bitfield_default },
- { "SDMA_UTCL1_RD_FIFO_SED", 4, 4, &umr_bitfield_default },
- { "SDMA_UTCL1_RDBST_FIFO_SED", 5, 5, &umr_bitfield_default },
- { "SDMA_DATA_LUT_FIFO_SED", 6, 6, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF0_SED", 7, 7, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF1_SED", 8, 8, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF2_SED", 9, 9, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF3_SED", 10, 10, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF4_SED", 11, 11, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF5_SED", 12, 12, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF6_SED", 13, 13, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF7_SED", 14, 14, &umr_bitfield_default },
- { "SDMA_SPLIT_DAT_BUF_SED", 15, 15, &umr_bitfield_default },
- { "SDMA_MC_WR_ADDR_FIFO_SED", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_EDC_COUNTER_CLEAR[] = {
- { "DUMMY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_STATUS2_REG[] = {
- { "ID", 0, 1, &umr_bitfield_default },
- { "F32_INSTR_PTR", 2, 11, &umr_bitfield_default },
- { "CMD_OP", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_ATOMIC_CNTL[] = {
- { "LOOP_TIMER", 0, 30, &umr_bitfield_default },
- { "ATOMIC_RTN_INT_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_ATOMIC_PREOP_LO[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_ATOMIC_PREOP_HI[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_CNTL[] = {
- { "REDO_ENABLE", 0, 0, &umr_bitfield_default },
- { "REDO_DELAY", 1, 10, &umr_bitfield_default },
- { "REDO_WATERMK", 11, 13, &umr_bitfield_default },
- { "INVACK_DELAY", 14, 23, &umr_bitfield_default },
- { "REQL2_CREDIT", 24, 28, &umr_bitfield_default },
- { "VADDR_WATERMK", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_WATERMK[] = {
- { "REQMC_WATERMK", 0, 9, &umr_bitfield_default },
- { "REQPG_WATERMK", 10, 17, &umr_bitfield_default },
- { "INVREQ_WATERMK", 18, 25, &umr_bitfield_default },
- { "XNACK_WATERMK", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_RD_STATUS[] = {
- { "RQMC_RET_ADDR_FIFO_EMPTY", 0, 0, &umr_bitfield_default },
- { "RQMC_REQ_FIFO_EMPTY", 1, 1, &umr_bitfield_default },
- { "RTPG_RET_BUF_EMPTY", 2, 2, &umr_bitfield_default },
- { "RTPG_VADDR_FIFO_EMPTY", 3, 3, &umr_bitfield_default },
- { "RQPG_HEAD_VIRT_FIFO_EMPTY", 4, 4, &umr_bitfield_default },
- { "RQPG_REDO_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
- { "RQPG_REQPAGE_FIFO_EMPTY", 6, 6, &umr_bitfield_default },
- { "RQPG_XNACK_FIFO_EMPTY", 7, 7, &umr_bitfield_default },
- { "RQPG_INVREQ_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
- { "RQMC_RET_ADDR_FIFO_FULL", 9, 9, &umr_bitfield_default },
- { "RQMC_REQ_FIFO_FULL", 10, 10, &umr_bitfield_default },
- { "RTPG_RET_BUF_FULL", 11, 11, &umr_bitfield_default },
- { "RTPG_VADDR_FIFO_FULL", 12, 12, &umr_bitfield_default },
- { "RQPG_HEAD_VIRT_FIFO_FULL", 13, 13, &umr_bitfield_default },
- { "RQPG_REDO_FIFO_FULL", 14, 14, &umr_bitfield_default },
- { "RQPG_REQPAGE_FIFO_FULL", 15, 15, &umr_bitfield_default },
- { "RQPG_XNACK_FIFO_FULL", 16, 16, &umr_bitfield_default },
- { "RQPG_INVREQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
- { "PAGE_FAULT", 18, 18, &umr_bitfield_default },
- { "PAGE_NULL", 19, 19, &umr_bitfield_default },
- { "REQL2_IDLE", 20, 20, &umr_bitfield_default },
- { "CE_L1_STALL", 21, 21, &umr_bitfield_default },
- { "NEXT_RD_VECTOR", 22, 25, &umr_bitfield_default },
- { "MERGE_STATE", 26, 28, &umr_bitfield_default },
- { "ADDR_RD_RTR", 29, 29, &umr_bitfield_default },
- { "WPTR_POLLING", 30, 30, &umr_bitfield_default },
- { "INVREQ_SIZE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_WR_STATUS[] = {
- { "RQMC_RET_ADDR_FIFO_EMPTY", 0, 0, &umr_bitfield_default },
- { "RQMC_REQ_FIFO_EMPTY", 1, 1, &umr_bitfield_default },
- { "RTPG_RET_BUF_EMPTY", 2, 2, &umr_bitfield_default },
- { "RTPG_VADDR_FIFO_EMPTY", 3, 3, &umr_bitfield_default },
- { "RQPG_HEAD_VIRT_FIFO_EMPTY", 4, 4, &umr_bitfield_default },
- { "RQPG_REDO_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
- { "RQPG_REQPAGE_FIFO_EMPTY", 6, 6, &umr_bitfield_default },
- { "RQPG_XNACK_FIFO_EMPTY", 7, 7, &umr_bitfield_default },
- { "RQPG_INVREQ_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
- { "RQMC_RET_ADDR_FIFO_FULL", 9, 9, &umr_bitfield_default },
- { "RQMC_REQ_FIFO_FULL", 10, 10, &umr_bitfield_default },
- { "RTPG_RET_BUF_FULL", 11, 11, &umr_bitfield_default },
- { "RTPG_VADDR_FIFO_FULL", 12, 12, &umr_bitfield_default },
- { "RQPG_HEAD_VIRT_FIFO_FULL", 13, 13, &umr_bitfield_default },
- { "RQPG_REDO_FIFO_FULL", 14, 14, &umr_bitfield_default },
- { "RQPG_REQPAGE_FIFO_FULL", 15, 15, &umr_bitfield_default },
- { "RQPG_XNACK_FIFO_FULL", 16, 16, &umr_bitfield_default },
- { "RQPG_INVREQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
- { "PAGE_FAULT", 18, 18, &umr_bitfield_default },
- { "PAGE_NULL", 19, 19, &umr_bitfield_default },
- { "REQL2_IDLE", 20, 20, &umr_bitfield_default },
- { "F32_WR_RTR", 21, 21, &umr_bitfield_default },
- { "NEXT_WR_VECTOR", 22, 24, &umr_bitfield_default },
- { "MERGE_STATE", 25, 27, &umr_bitfield_default },
- { "RPTR_DATA_FIFO_EMPTY", 28, 28, &umr_bitfield_default },
- { "RPTR_DATA_FIFO_FULL", 29, 29, &umr_bitfield_default },
- { "WRREQ_DATA_FIFO_EMPTY", 30, 30, &umr_bitfield_default },
- { "WRREQ_DATA_FIFO_FULL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_INV0[] = {
- { "INV_MIDDLE", 0, 0, &umr_bitfield_default },
- { "RD_TIMEOUT", 1, 1, &umr_bitfield_default },
- { "WR_TIMEOUT", 2, 2, &umr_bitfield_default },
- { "RD_IN_INVADR", 3, 3, &umr_bitfield_default },
- { "WR_IN_INVADR", 4, 4, &umr_bitfield_default },
- { "PAGE_NULL_SW", 5, 5, &umr_bitfield_default },
- { "XNACK_IS_INVADR", 6, 6, &umr_bitfield_default },
- { "INVREQ_ENABLE", 7, 7, &umr_bitfield_default },
- { "NACK_TIMEOUT_SW", 8, 8, &umr_bitfield_default },
- { "NFLUSH_INV_IDLE", 9, 9, &umr_bitfield_default },
- { "FLUSH_INV_IDLE", 10, 10, &umr_bitfield_default },
- { "INV_FLUSHTYPE", 11, 11, &umr_bitfield_default },
- { "INV_VMID_VEC", 12, 27, &umr_bitfield_default },
- { "INV_ADDR_HI", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_INV1[] = {
- { "INV_ADDR_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_INV2[] = {
- { "INV_NFLUSH_VMID_VEC", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_RD_XNACK0[] = {
- { "XNACK_ADDR_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_RD_XNACK1[] = {
- { "XNACK_ADDR_HI", 0, 3, &umr_bitfield_default },
- { "XNACK_VMID", 4, 7, &umr_bitfield_default },
- { "XNACK_VECTOR", 8, 25, &umr_bitfield_default },
- { "IS_XNACK", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_WR_XNACK0[] = {
- { "XNACK_ADDR_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_WR_XNACK1[] = {
- { "XNACK_ADDR_HI", 0, 3, &umr_bitfield_default },
- { "XNACK_VMID", 4, 7, &umr_bitfield_default },
- { "XNACK_VECTOR", 8, 25, &umr_bitfield_default },
- { "IS_XNACK", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_TIMEOUT[] = {
- { "RD_XNACK_LIMIT", 0, 15, &umr_bitfield_default },
- { "WR_XNACK_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UTCL1_PAGE[] = {
- { "VM_HOLE", 0, 0, &umr_bitfield_default },
- { "REQ_TYPE", 1, 4, &umr_bitfield_default },
- { "USE_MTYPE", 6, 8, &umr_bitfield_default },
- { "USE_PT_SNOOP", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_POWER_CNTL_IDLE[] = {
- { "DELAY0", 0, 15, &umr_bitfield_default },
- { "DELAY1", 16, 23, &umr_bitfield_default },
- { "DELAY2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RELAX_ORDERING_LUT[] = {
- { "RESERVED0", 0, 0, &umr_bitfield_default },
- { "COPY", 1, 1, &umr_bitfield_default },
- { "WRITE", 2, 2, &umr_bitfield_default },
- { "RESERVED3", 3, 3, &umr_bitfield_default },
- { "RESERVED4", 4, 4, &umr_bitfield_default },
- { "FENCE", 5, 5, &umr_bitfield_default },
- { "RESERVED76", 6, 7, &umr_bitfield_default },
- { "POLL_MEM", 8, 8, &umr_bitfield_default },
- { "COND_EXE", 9, 9, &umr_bitfield_default },
- { "ATOMIC", 10, 10, &umr_bitfield_default },
- { "CONST_FILL", 11, 11, &umr_bitfield_default },
- { "PTEPDE", 12, 12, &umr_bitfield_default },
- { "TIMESTAMP", 13, 13, &umr_bitfield_default },
- { "RESERVED", 14, 26, &umr_bitfield_default },
- { "WORLD_SWITCH", 27, 27, &umr_bitfield_default },
- { "RPTR_WRB", 28, 28, &umr_bitfield_default },
- { "WPTR_POLL", 29, 29, &umr_bitfield_default },
- { "IB_FETCH", 30, 30, &umr_bitfield_default },
- { "RB_FETCH", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CHICKEN_BITS_2[] = {
- { "F32_CMD_PROC_DELAY", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_STATUS3_REG[] = {
- { "CMD_OP_STATUS", 0, 15, &umr_bitfield_default },
- { "PREV_VM_CMD", 16, 19, &umr_bitfield_default },
- { "EXCEPTION_IDLE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PHYSICAL_ADDR_LO[] = {
- { "D_VALID", 0, 0, &umr_bitfield_default },
- { "DIRTY", 1, 1, &umr_bitfield_default },
- { "PHY_VALID", 2, 2, &umr_bitfield_default },
- { "ADDR", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PHYSICAL_ADDR_HI[] = {
- { "ADDR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PHASE2_QUANTUM[] = {
- { "UNIT", 0, 3, &umr_bitfield_default },
- { "VALUE", 8, 23, &umr_bitfield_default },
- { "PREFER", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_ERROR_LOG[] = {
- { "OVERRIDE", 0, 15, &umr_bitfield_default },
- { "STATUS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG0[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG1[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG2[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG3[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_F32_COUNTER[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_UNBREAKABLE[] = {
- { "VALUE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PERFMON_CNTL[] = {
- { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
- { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
- { "PERF_SEL0", 2, 9, &umr_bitfield_default },
- { "PERF_ENABLE1", 10, 10, &umr_bitfield_default },
- { "PERF_CLEAR1", 11, 11, &umr_bitfield_default },
- { "PERF_SEL1", 12, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PERFCOUNTER0_RESULT[] = {
- { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PERFCOUNTER1_RESULT[] = {
- { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE[] = {
- { "RANGE_LOW", 0, 13, &umr_bitfield_default },
- { "RANGE_HIGH", 14, 27, &umr_bitfield_default },
- { "SELECT_RW", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_CRD_CNTL[] = {
- { "MC_WRREQ_CREDIT", 7, 12, &umr_bitfield_default },
- { "MC_RDREQ_CREDIT", 13, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_MMHUB_TRUSTLVL[] = {
- { "SECFLAG0", 0, 2, &umr_bitfield_default },
- { "SECFLAG1", 3, 5, &umr_bitfield_default },
- { "SECFLAG2", 6, 8, &umr_bitfield_default },
- { "SECFLAG3", 9, 11, &umr_bitfield_default },
- { "SECFLAG4", 12, 14, &umr_bitfield_default },
- { "SECFLAG5", 15, 17, &umr_bitfield_default },
- { "SECFLAG6", 18, 20, &umr_bitfield_default },
- { "SECFLAG7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GPU_IOV_VIOLATION_LOG[] = {
- { "VIOLATION_STATUS", 0, 0, &umr_bitfield_default },
- { "MULTIPLE_VIOLATION_STATUS", 1, 1, &umr_bitfield_default },
- { "ADDRESS", 2, 17, &umr_bitfield_default },
- { "WRITE_OPERATION", 18, 18, &umr_bitfield_default },
- { "VF", 19, 19, &umr_bitfield_default },
- { "VFID", 20, 23, &umr_bitfield_default },
- { "INITIATOR_ID", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_ULV_CNTL[] = {
- { "HYSTERESIS", 0, 4, &umr_bitfield_default },
- { "ENTER_ULV_INT", 29, 29, &umr_bitfield_default },
- { "EXIT_ULV_INT", 30, 30, &umr_bitfield_default },
- { "ULV_STATUS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_EA_DBIT_ADDR_DATA[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_EA_DBIT_ADDR_INDEX[] = {
- { "VALUE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_CNTL[] = {
- { "RB_ENABLE", 0, 0, &umr_bitfield_default },
- { "RB_SIZE", 1, 6, &umr_bitfield_default },
- { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
- { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
- { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
- { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
- { "RB_PRIV", 23, 23, &umr_bitfield_default },
- { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_BASE[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_BASE_HI[] = {
- { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_RPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_WPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_CNTL[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
- { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
- { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
- { "FREQUENCY", 4, 15, &umr_bitfield_default },
- { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_CNTL[] = {
- { "IB_ENABLE", 0, 0, &umr_bitfield_default },
- { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
- { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
- { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_RPTR[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_OFFSET[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_BASE_LO[] = {
- { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_BASE_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_SIZE[] = {
- { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_SKIP_CNTL[] = {
- { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_CONTEXT_STATUS[] = {
- { "SELECTED", 0, 0, &umr_bitfield_default },
- { "IDLE", 2, 2, &umr_bitfield_default },
- { "EXPIRED", 3, 3, &umr_bitfield_default },
- { "EXCEPTION", 4, 6, &umr_bitfield_default },
- { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
- { "CTXSW_READY", 8, 8, &umr_bitfield_default },
- { "PREEMPTED", 9, 9, &umr_bitfield_default },
- { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_DOORBELL[] = {
- { "ENABLE", 28, 28, &umr_bitfield_default },
- { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_CONTEXT_CNTL[] = {
- { "RESUME_CTX", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_STATUS[] = {
- { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
- { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_DOORBELL_LOG[] = {
- { "BE_ERROR", 0, 0, &umr_bitfield_default },
- { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_WATERMARK[] = {
- { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
- { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_DOORBELL_OFFSET[] = {
- { "OFFSET", 2, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_CSA_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_CSA_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_IB_SUB_REMAIN[] = {
- { "SIZE", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_PREEMPT[] = {
- { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_DUMMY_REG[] = {
- { "DUMMY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_RB_AQL_CNTL[] = {
- { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
- { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
- { "PACKET_STEP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MINOR_PTR_UPDATE[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA0[] = {
- { "DATA0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA1[] = {
- { "DATA1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA2[] = {
- { "DATA2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA3[] = {
- { "DATA3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA4[] = {
- { "DATA4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA5[] = {
- { "DATA5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA6[] = {
- { "DATA6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA7[] = {
- { "DATA7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA8[] = {
- { "DATA8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_GFX_MIDCMD_CNTL[] = {
- { "DATA_VALID", 0, 0, &umr_bitfield_default },
- { "COPY_MODE", 1, 1, &umr_bitfield_default },
- { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
- { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_CNTL[] = {
- { "RB_ENABLE", 0, 0, &umr_bitfield_default },
- { "RB_SIZE", 1, 6, &umr_bitfield_default },
- { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
- { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
- { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
- { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
- { "RB_PRIV", 23, 23, &umr_bitfield_default },
- { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_BASE[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_BASE_HI[] = {
- { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_RPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_RPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_WPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_WPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_WPTR_POLL_CNTL[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
- { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
- { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
- { "FREQUENCY", 4, 15, &umr_bitfield_default },
- { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_RPTR_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_RPTR_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_IB_CNTL[] = {
- { "IB_ENABLE", 0, 0, &umr_bitfield_default },
- { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
- { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
- { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_IB_RPTR[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_IB_OFFSET[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_IB_BASE_LO[] = {
- { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_IB_BASE_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_IB_SIZE[] = {
- { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_SKIP_CNTL[] = {
- { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_CONTEXT_STATUS[] = {
- { "SELECTED", 0, 0, &umr_bitfield_default },
- { "IDLE", 2, 2, &umr_bitfield_default },
- { "EXPIRED", 3, 3, &umr_bitfield_default },
- { "EXCEPTION", 4, 6, &umr_bitfield_default },
- { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
- { "CTXSW_READY", 8, 8, &umr_bitfield_default },
- { "PREEMPTED", 9, 9, &umr_bitfield_default },
- { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_DOORBELL[] = {
- { "ENABLE", 28, 28, &umr_bitfield_default },
- { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_STATUS[] = {
- { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
- { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_DOORBELL_LOG[] = {
- { "BE_ERROR", 0, 0, &umr_bitfield_default },
- { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_WATERMARK[] = {
- { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
- { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_DOORBELL_OFFSET[] = {
- { "OFFSET", 2, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_CSA_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_CSA_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_IB_SUB_REMAIN[] = {
- { "SIZE", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_PREEMPT[] = {
- { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_DUMMY_REG[] = {
- { "DUMMY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_RB_AQL_CNTL[] = {
- { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
- { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
- { "PACKET_STEP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MINOR_PTR_UPDATE[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA0[] = {
- { "DATA0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA1[] = {
- { "DATA1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA2[] = {
- { "DATA2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA3[] = {
- { "DATA3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA4[] = {
- { "DATA4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA5[] = {
- { "DATA5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA6[] = {
- { "DATA6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA7[] = {
- { "DATA7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA8[] = {
- { "DATA8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_CNTL[] = {
- { "DATA_VALID", 0, 0, &umr_bitfield_default },
- { "COPY_MODE", 1, 1, &umr_bitfield_default },
- { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
- { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_CNTL[] = {
- { "RB_ENABLE", 0, 0, &umr_bitfield_default },
- { "RB_SIZE", 1, 6, &umr_bitfield_default },
- { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
- { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
- { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
- { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
- { "RB_PRIV", 23, 23, &umr_bitfield_default },
- { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_BASE[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_BASE_HI[] = {
- { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
- { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
- { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
- { "FREQUENCY", 4, 15, &umr_bitfield_default },
- { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_CNTL[] = {
- { "IB_ENABLE", 0, 0, &umr_bitfield_default },
- { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
- { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
- { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_RPTR[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_OFFSET[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_LO[] = {
- { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_SIZE[] = {
- { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_SKIP_CNTL[] = {
- { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_CONTEXT_STATUS[] = {
- { "SELECTED", 0, 0, &umr_bitfield_default },
- { "IDLE", 2, 2, &umr_bitfield_default },
- { "EXPIRED", 3, 3, &umr_bitfield_default },
- { "EXCEPTION", 4, 6, &umr_bitfield_default },
- { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
- { "CTXSW_READY", 8, 8, &umr_bitfield_default },
- { "PREEMPTED", 9, 9, &umr_bitfield_default },
- { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_DOORBELL[] = {
- { "ENABLE", 28, 28, &umr_bitfield_default },
- { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_STATUS[] = {
- { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
- { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_DOORBELL_LOG[] = {
- { "BE_ERROR", 0, 0, &umr_bitfield_default },
- { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_WATERMARK[] = {
- { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
- { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_DOORBELL_OFFSET[] = {
- { "OFFSET", 2, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_CSA_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_CSA_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_IB_SUB_REMAIN[] = {
- { "SIZE", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_PREEMPT[] = {
- { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_DUMMY_REG[] = {
- { "DUMMY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_RB_AQL_CNTL[] = {
- { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
- { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
- { "PACKET_STEP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MINOR_PTR_UPDATE[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA0[] = {
- { "DATA0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA1[] = {
- { "DATA1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA2[] = {
- { "DATA2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA3[] = {
- { "DATA3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA4[] = {
- { "DATA4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA5[] = {
- { "DATA5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA6[] = {
- { "DATA6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA7[] = {
- { "DATA7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA8[] = {
- { "DATA8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_CNTL[] = {
- { "DATA_VALID", 0, 0, &umr_bitfield_default },
- { "COPY_MODE", 1, 1, &umr_bitfield_default },
- { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
- { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_CNTL[] = {
- { "RB_ENABLE", 0, 0, &umr_bitfield_default },
- { "RB_SIZE", 1, 6, &umr_bitfield_default },
- { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
- { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
- { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
- { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
- { "RB_PRIV", 23, 23, &umr_bitfield_default },
- { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_BASE[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_BASE_HI[] = {
- { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
- { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
- { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
- { "FREQUENCY", 4, 15, &umr_bitfield_default },
- { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_CNTL[] = {
- { "IB_ENABLE", 0, 0, &umr_bitfield_default },
- { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
- { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
- { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_RPTR[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_OFFSET[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_LO[] = {
- { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_SIZE[] = {
- { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_SKIP_CNTL[] = {
- { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_CONTEXT_STATUS[] = {
- { "SELECTED", 0, 0, &umr_bitfield_default },
- { "IDLE", 2, 2, &umr_bitfield_default },
- { "EXPIRED", 3, 3, &umr_bitfield_default },
- { "EXCEPTION", 4, 6, &umr_bitfield_default },
- { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
- { "CTXSW_READY", 8, 8, &umr_bitfield_default },
- { "PREEMPTED", 9, 9, &umr_bitfield_default },
- { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_DOORBELL[] = {
- { "ENABLE", 28, 28, &umr_bitfield_default },
- { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_STATUS[] = {
- { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
- { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_DOORBELL_LOG[] = {
- { "BE_ERROR", 0, 0, &umr_bitfield_default },
- { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_WATERMARK[] = {
- { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
- { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_DOORBELL_OFFSET[] = {
- { "OFFSET", 2, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_CSA_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_CSA_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_IB_SUB_REMAIN[] = {
- { "SIZE", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_PREEMPT[] = {
- { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_DUMMY_REG[] = {
- { "DUMMY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_RB_AQL_CNTL[] = {
- { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
- { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
- { "PACKET_STEP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MINOR_PTR_UPDATE[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA0[] = {
- { "DATA0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA1[] = {
- { "DATA1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA2[] = {
- { "DATA2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA3[] = {
- { "DATA3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA4[] = {
- { "DATA4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA5[] = {
- { "DATA5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA6[] = {
- { "DATA6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA7[] = {
- { "DATA7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA8[] = {
- { "DATA8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_CNTL[] = {
- { "DATA_VALID", 0, 0, &umr_bitfield_default },
- { "COPY_MODE", 1, 1, &umr_bitfield_default },
- { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
- { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
};
diff --git a/src/lib/ip/sdma140_bits.i b/src/lib/ip/sdma140_bits.i
index 7e0124b13077..b8e81e85ea75 100644
--- a/src/lib/ip/sdma140_bits.i
+++ b/src/lib/ip/sdma140_bits.i
@@ -1,1274 +1,510 @@
static struct umr_bitfield mmSDMA1_UCODE_ADDR[] = {
- { "VALUE", 0, 12, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UCODE_DATA[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_VM_CNTL[] = {
- { "CMD", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_VM_CTX_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_VM_CTX_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_ACTIVE_FCN_ID[] = {
- { "VFID", 0, 3, &umr_bitfield_default },
- { "RESERVED", 4, 30, &umr_bitfield_default },
- { "VF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_VM_CTX_CNTL[] = {
- { "PRIV", 0, 0, &umr_bitfield_default },
- { "VMID", 4, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_VIRT_RESET_REQ[] = {
- { "VF", 0, 15, &umr_bitfield_default },
- { "PF", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_VF_ENABLE[] = {
- { "VF_ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE0[] = {
- { "SDMA1_GFX_RB_CNTL", 0, 0, &umr_bitfield_default },
- { "SDMA1_GFX_RB_BASE", 1, 1, &umr_bitfield_default },
- { "SDMA1_GFX_RB_BASE_HI", 2, 2, &umr_bitfield_default },
- { "SDMA1_GFX_RB_RPTR", 3, 3, &umr_bitfield_default },
- { "SDMA1_GFX_RB_RPTR_HI", 4, 4, &umr_bitfield_default },
- { "SDMA1_GFX_RB_WPTR", 5, 5, &umr_bitfield_default },
- { "SDMA1_GFX_RB_WPTR_HI", 6, 6, &umr_bitfield_default },
- { "SDMA1_GFX_RB_WPTR_POLL_CNTL", 7, 7, &umr_bitfield_default },
- { "SDMA1_GFX_RB_RPTR_ADDR_HI", 8, 8, &umr_bitfield_default },
- { "SDMA1_GFX_RB_RPTR_ADDR_LO", 9, 9, &umr_bitfield_default },
- { "SDMA1_GFX_IB_CNTL", 10, 10, &umr_bitfield_default },
- { "SDMA1_GFX_IB_RPTR", 11, 11, &umr_bitfield_default },
- { "SDMA1_GFX_IB_OFFSET", 12, 12, &umr_bitfield_default },
- { "SDMA1_GFX_IB_BASE_LO", 13, 13, &umr_bitfield_default },
- { "SDMA1_GFX_IB_BASE_HI", 14, 14, &umr_bitfield_default },
- { "SDMA1_GFX_IB_SIZE", 15, 15, &umr_bitfield_default },
- { "SDMA1_GFX_SKIP_CNTL", 16, 16, &umr_bitfield_default },
- { "SDMA1_GFX_CONTEXT_STATUS", 17, 17, &umr_bitfield_default },
- { "SDMA1_GFX_DOORBELL", 18, 18, &umr_bitfield_default },
- { "SDMA1_GFX_CONTEXT_CNTL", 19, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE1[] = {
- { "SDMA1_GFX_STATUS", 8, 8, &umr_bitfield_default },
- { "SDMA1_GFX_DOORBELL_LOG", 9, 9, &umr_bitfield_default },
- { "SDMA1_GFX_WATERMARK", 10, 10, &umr_bitfield_default },
- { "SDMA1_GFX_DOORBELL_OFFSET", 11, 11, &umr_bitfield_default },
- { "SDMA1_GFX_CSA_ADDR_LO", 12, 12, &umr_bitfield_default },
- { "SDMA1_GFX_CSA_ADDR_HI", 13, 13, &umr_bitfield_default },
- { "VOID_REG2", 14, 14, &umr_bitfield_default },
- { "SDMA1_GFX_IB_SUB_REMAIN", 15, 15, &umr_bitfield_default },
- { "SDMA1_GFX_PREEMPT", 16, 16, &umr_bitfield_default },
- { "SDMA1_GFX_DUMMY_REG", 17, 17, &umr_bitfield_default },
- { "SDMA1_GFX_RB_WPTR_POLL_ADDR_HI", 18, 18, &umr_bitfield_default },
- { "SDMA1_GFX_RB_WPTR_POLL_ADDR_LO", 19, 19, &umr_bitfield_default },
- { "SDMA1_GFX_RB_AQL_CNTL", 20, 20, &umr_bitfield_default },
- { "SDMA1_GFX_MINOR_PTR_UPDATE", 21, 21, &umr_bitfield_default },
- { "RESERVED", 22, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE2[] = {
- { "SDMA1_GFX_MIDCMD_DATA0", 0, 0, &umr_bitfield_default },
- { "SDMA1_GFX_MIDCMD_DATA1", 1, 1, &umr_bitfield_default },
- { "SDMA1_GFX_MIDCMD_DATA2", 2, 2, &umr_bitfield_default },
- { "SDMA1_GFX_MIDCMD_DATA3", 3, 3, &umr_bitfield_default },
- { "SDMA1_GFX_MIDCMD_DATA4", 4, 4, &umr_bitfield_default },
- { "SDMA1_GFX_MIDCMD_DATA5", 5, 5, &umr_bitfield_default },
- { "SDMA1_GFX_MIDCMD_DATA6", 6, 6, &umr_bitfield_default },
- { "SDMA1_GFX_MIDCMD_DATA7", 7, 7, &umr_bitfield_default },
- { "SDMA1_GFX_MIDCMD_DATA8", 8, 8, &umr_bitfield_default },
- { "SDMA1_GFX_MIDCMD_CNTL", 9, 9, &umr_bitfield_default },
- { "RESERVED", 10, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE3[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PUB_REG_TYPE0[] = {
- { "SDMA1_UCODE_ADDR", 0, 0, &umr_bitfield_default },
- { "SDMA1_UCODE_DATA", 1, 1, &umr_bitfield_default },
- { "RESERVED3", 3, 3, &umr_bitfield_default },
- { "SDMA1_VM_CNTL", 4, 4, &umr_bitfield_default },
- { "SDMA1_VM_CTX_LO", 5, 5, &umr_bitfield_default },
- { "SDMA1_VM_CTX_HI", 6, 6, &umr_bitfield_default },
- { "SDMA1_ACTIVE_FCN_ID", 7, 7, &umr_bitfield_default },
- { "SDMA1_VM_CTX_CNTL", 8, 8, &umr_bitfield_default },
- { "SDMA1_VIRT_RESET_REQ", 9, 9, &umr_bitfield_default },
- { "RESERVED10", 10, 10, &umr_bitfield_default },
- { "SDMA1_CONTEXT_REG_TYPE0", 11, 11, &umr_bitfield_default },
- { "SDMA1_CONTEXT_REG_TYPE1", 12, 12, &umr_bitfield_default },
- { "SDMA1_CONTEXT_REG_TYPE2", 13, 13, &umr_bitfield_default },
- { "SDMA1_CONTEXT_REG_TYPE3", 14, 14, &umr_bitfield_default },
- { "SDMA1_PUB_REG_TYPE0", 15, 15, &umr_bitfield_default },
- { "SDMA1_PUB_REG_TYPE1", 16, 16, &umr_bitfield_default },
- { "SDMA1_PUB_REG_TYPE2", 17, 17, &umr_bitfield_default },
- { "SDMA1_PUB_REG_TYPE3", 18, 18, &umr_bitfield_default },
- { "SDMA1_MMHUB_CNTL", 19, 19, &umr_bitfield_default },
- { "RESERVED_FOR_PSPSMU_ACCESS_ONLY", 20, 24, &umr_bitfield_default },
- { "SDMA1_CONTEXT_GROUP_BOUNDARY", 25, 25, &umr_bitfield_default },
- { "SDMA1_POWER_CNTL", 26, 26, &umr_bitfield_default },
- { "SDMA1_CLK_CTRL", 27, 27, &umr_bitfield_default },
- { "SDMA1_CNTL", 28, 28, &umr_bitfield_default },
- { "SDMA1_CHICKEN_BITS", 29, 29, &umr_bitfield_default },
- { "SDMA1_GB_ADDR_CONFIG", 30, 30, &umr_bitfield_default },
- { "SDMA1_GB_ADDR_CONFIG_READ", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PUB_REG_TYPE1[] = {
- { "SDMA1_RB_RPTR_FETCH_HI", 0, 0, &umr_bitfield_default },
- { "SDMA1_SEM_WAIT_FAIL_TIMER_CNTL", 1, 1, &umr_bitfield_default },
- { "SDMA1_RB_RPTR_FETCH", 2, 2, &umr_bitfield_default },
- { "SDMA1_IB_OFFSET_FETCH", 3, 3, &umr_bitfield_default },
- { "SDMA1_PROGRAM", 4, 4, &umr_bitfield_default },
- { "SDMA1_STATUS_REG", 5, 5, &umr_bitfield_default },
- { "SDMA1_STATUS1_REG", 6, 6, &umr_bitfield_default },
- { "SDMA1_RD_BURST_CNTL", 7, 7, &umr_bitfield_default },
- { "SDMA1_HBM_PAGE_CONFIG", 8, 8, &umr_bitfield_default },
- { "SDMA1_UCODE_CHECKSUM", 9, 9, &umr_bitfield_default },
- { "SDMA1_F32_CNTL", 10, 10, &umr_bitfield_default },
- { "SDMA1_FREEZE", 11, 11, &umr_bitfield_default },
- { "SDMA1_PHASE0_QUANTUM", 12, 12, &umr_bitfield_default },
- { "SDMA1_PHASE1_QUANTUM", 13, 13, &umr_bitfield_default },
- { "SDMA_POWER_GATING", 14, 14, &umr_bitfield_default },
- { "SDMA_PGFSM_CONFIG", 15, 15, &umr_bitfield_default },
- { "SDMA_PGFSM_WRITE", 16, 16, &umr_bitfield_default },
- { "SDMA_PGFSM_READ", 17, 17, &umr_bitfield_default },
- { "SDMA1_EDC_CONFIG", 18, 18, &umr_bitfield_default },
- { "SDMA1_BA_THRESHOLD", 19, 19, &umr_bitfield_default },
- { "SDMA1_ID", 20, 20, &umr_bitfield_default },
- { "SDMA1_VERSION", 21, 21, &umr_bitfield_default },
- { "SDMA1_EDC_COUNTER", 22, 22, &umr_bitfield_default },
- { "SDMA1_EDC_COUNTER_CLEAR", 23, 23, &umr_bitfield_default },
- { "SDMA1_STATUS2_REG", 24, 24, &umr_bitfield_default },
- { "SDMA1_ATOMIC_CNTL", 25, 25, &umr_bitfield_default },
- { "SDMA1_ATOMIC_PREOP_LO", 26, 26, &umr_bitfield_default },
- { "SDMA1_ATOMIC_PREOP_HI", 27, 27, &umr_bitfield_default },
- { "SDMA1_UTCL1_CNTL", 28, 28, &umr_bitfield_default },
- { "SDMA1_UTCL1_WATERMK", 29, 29, &umr_bitfield_default },
- { "SDMA1_UTCL1_RD_STATUS", 30, 30, &umr_bitfield_default },
- { "SDMA1_UTCL1_WR_STATUS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PUB_REG_TYPE2[] = {
- { "SDMA1_UTCL1_INV0", 0, 0, &umr_bitfield_default },
- { "SDMA1_UTCL1_INV1", 1, 1, &umr_bitfield_default },
- { "SDMA1_UTCL1_INV2", 2, 2, &umr_bitfield_default },
- { "SDMA1_UTCL1_RD_XNACK0", 3, 3, &umr_bitfield_default },
- { "SDMA1_UTCL1_RD_XNACK1", 4, 4, &umr_bitfield_default },
- { "SDMA1_UTCL1_WR_XNACK0", 5, 5, &umr_bitfield_default },
- { "SDMA1_UTCL1_WR_XNACK1", 6, 6, &umr_bitfield_default },
- { "SDMA1_UTCL1_TIMEOUT", 7, 7, &umr_bitfield_default },
- { "SDMA1_UTCL1_PAGE", 8, 8, &umr_bitfield_default },
- { "SDMA1_POWER_CNTL_IDLE", 9, 9, &umr_bitfield_default },
- { "SDMA1_RELAX_ORDERING_LUT", 10, 10, &umr_bitfield_default },
- { "SDMA1_CHICKEN_BITS_2", 11, 11, &umr_bitfield_default },
- { "SDMA1_STATUS3_REG", 12, 12, &umr_bitfield_default },
- { "SDMA1_PHYSICAL_ADDR_LO", 13, 13, &umr_bitfield_default },
- { "SDMA1_PHYSICAL_ADDR_HI", 14, 14, &umr_bitfield_default },
- { "SDMA1_PHASE2_QUANTUM", 15, 15, &umr_bitfield_default },
- { "SDMA1_ERROR_LOG", 16, 16, &umr_bitfield_default },
- { "SDMA1_PUB_DUMMY_REG0", 17, 17, &umr_bitfield_default },
- { "SDMA1_PUB_DUMMY_REG1", 18, 18, &umr_bitfield_default },
- { "SDMA1_PUB_DUMMY_REG2", 19, 19, &umr_bitfield_default },
- { "SDMA1_PUB_DUMMY_REG3", 20, 20, &umr_bitfield_default },
- { "SDMA1_F32_COUNTER", 21, 21, &umr_bitfield_default },
- { "SDMA1_UNBREAKABLE", 22, 22, &umr_bitfield_default },
- { "SDMA1_PERFMON_CNTL", 23, 23, &umr_bitfield_default },
- { "SDMA1_PERFCOUNTER0_RESULT", 24, 24, &umr_bitfield_default },
- { "SDMA1_PERFCOUNTER1_RESULT", 25, 25, &umr_bitfield_default },
- { "SDMA1_PERFCOUNTER_TAG_DELAY_RANGE", 26, 26, &umr_bitfield_default },
- { "SDMA1_CRD_CNTL", 27, 27, &umr_bitfield_default },
- { "SDMA1_MMHUB_TRUSTLVL", 28, 28, &umr_bitfield_default },
- { "SDMA1_GPU_IOV_VIOLATION_LOG", 29, 29, &umr_bitfield_default },
- { "SDMA1_ULV_CNTL", 30, 30, &umr_bitfield_default },
- { "RESERVED", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PUB_REG_TYPE3[] = {
- { "SDMA1_EA_DBIT_ADDR_DATA", 0, 0, &umr_bitfield_default },
- { "SDMA1_EA_DBIT_ADDR_INDEX", 1, 1, &umr_bitfield_default },
- { "RESERVED", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_MMHUB_CNTL[] = {
- { "UNIT_ID", 0, 5, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CONTEXT_GROUP_BOUNDARY[] = {
- { "RESERVED", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_POWER_CNTL[] = {
- { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default },
- { "MEM_POWER_LS_EN", 9, 9, &umr_bitfield_default },
- { "MEM_POWER_DS_EN", 10, 10, &umr_bitfield_default },
- { "MEM_POWER_SD_EN", 11, 11, &umr_bitfield_default },
- { "MEM_POWER_DELAY", 12, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CLK_CTRL[] = {
- { "ON_DELAY", 0, 3, &umr_bitfield_default },
- { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
- { "RESERVED", 12, 23, &umr_bitfield_default },
- { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
- { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
- { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
- { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
- { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
- { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
- { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
- { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CNTL[] = {
- { "TRAP_ENABLE", 0, 0, &umr_bitfield_default },
- { "UTC_L1_ENABLE", 1, 1, &umr_bitfield_default },
- { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default },
- { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default },
- { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
- { "MIDCMD_PREEMPT_ENABLE", 5, 5, &umr_bitfield_default },
- { "MIDCMD_WORLDSWITCH_ENABLE", 17, 17, &umr_bitfield_default },
- { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default },
- { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default },
- { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default },
- { "IB_PREEMPT_INT_ENABLE", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CHICKEN_BITS[] = {
- { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default },
- { "STALL_ON_TRANS_FULL_ENABLE", 1, 1, &umr_bitfield_default },
- { "STALL_ON_NO_FREE_DATA_BUFFER_ENABLE", 2, 2, &umr_bitfield_default },
- { "WRITE_BURST_LENGTH", 8, 9, &umr_bitfield_default },
- { "WRITE_BURST_WAIT_CYCLE", 10, 12, &umr_bitfield_default },
- { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default },
- { "RAW_CHECK_ENABLE", 17, 17, &umr_bitfield_default },
- { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default },
- { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default },
- { "TIME_BASED_QOS", 25, 25, &umr_bitfield_default },
- { "CE_AFIFO_WATERMARK", 26, 27, &umr_bitfield_default },
- { "CE_DFIFO_WATERMARK", 28, 29, &umr_bitfield_default },
- { "CE_LFIFO_WATERMARK", 30, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GB_ADDR_CONFIG[] = {
- { "NUM_PIPES", 0, 2, &umr_bitfield_default },
- { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default },
- { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
- { "NUM_BANKS", 12, 14, &umr_bitfield_default },
- { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GB_ADDR_CONFIG_READ[] = {
- { "NUM_PIPES", 0, 2, &umr_bitfield_default },
- { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default },
- { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
- { "NUM_BANKS", 12, 14, &umr_bitfield_default },
- { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RB_RPTR_FETCH_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[] = {
- { "TIMER", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RB_RPTR_FETCH[] = {
- { "OFFSET", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_IB_OFFSET_FETCH[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PROGRAM[] = {
- { "STREAM", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_STATUS_REG[] = {
- { "IDLE", 0, 0, &umr_bitfield_default },
- { "REG_IDLE", 1, 1, &umr_bitfield_default },
- { "RB_EMPTY", 2, 2, &umr_bitfield_default },
- { "RB_FULL", 3, 3, &umr_bitfield_default },
- { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default },
- { "RB_CMD_FULL", 5, 5, &umr_bitfield_default },
- { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default },
- { "IB_CMD_FULL", 7, 7, &umr_bitfield_default },
- { "BLOCK_IDLE", 8, 8, &umr_bitfield_default },
- { "INSIDE_IB", 9, 9, &umr_bitfield_default },
- { "EX_IDLE", 10, 10, &umr_bitfield_default },
- { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default },
- { "PACKET_READY", 12, 12, &umr_bitfield_default },
- { "MC_WR_IDLE", 13, 13, &umr_bitfield_default },
- { "SRBM_IDLE", 14, 14, &umr_bitfield_default },
- { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default },
- { "DELTA_RPTR_FULL", 16, 16, &umr_bitfield_default },
- { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default },
- { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default },
- { "MC_RD_IDLE", 19, 19, &umr_bitfield_default },
- { "DELTA_RPTR_EMPTY", 20, 20, &umr_bitfield_default },
- { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default },
- { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default },
- { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default },
- { "SEM_IDLE", 26, 26, &umr_bitfield_default },
- { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default },
- { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default },
- { "INT_IDLE", 30, 30, &umr_bitfield_default },
- { "INT_REQ_STALL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_STATUS1_REG[] = {
- { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default },
- { "CE_WR_IDLE", 1, 1, &umr_bitfield_default },
- { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default },
- { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default },
- { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default },
- { "CE_IN_IDLE", 5, 5, &umr_bitfield_default },
- { "CE_DST_IDLE", 6, 6, &umr_bitfield_default },
- { "CE_CMD_IDLE", 9, 9, &umr_bitfield_default },
- { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default },
- { "CE_INFO_FULL", 13, 13, &umr_bitfield_default },
- { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default },
- { "EX_START", 15, 15, &umr_bitfield_default },
- { "CE_RD_STALL", 17, 17, &umr_bitfield_default },
- { "CE_WR_STALL", 18, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RD_BURST_CNTL[] = {
- { "RD_BURST", 0, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_HBM_PAGE_CONFIG[] = {
- { "PAGE_SIZE_EXPONENT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UCODE_CHECKSUM[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_F32_CNTL[] = {
- { "HALT", 0, 0, &umr_bitfield_default },
- { "STEP", 1, 1, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_FREEZE[] = {
- { "PREEMPT", 0, 0, &umr_bitfield_default },
- { "FREEZE", 4, 4, &umr_bitfield_default },
- { "FROZEN", 5, 5, &umr_bitfield_default },
- { "F32_FREEZE", 6, 6, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PHASE0_QUANTUM[] = {
- { "UNIT", 0, 3, &umr_bitfield_default },
- { "VALUE", 8, 23, &umr_bitfield_default },
- { "PREFER", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PHASE1_QUANTUM[] = {
- { "UNIT", 0, 3, &umr_bitfield_default },
- { "VALUE", 8, 23, &umr_bitfield_default },
- { "PREFER", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_EDC_CONFIG[] = {
- { "DIS_EDC", 1, 1, &umr_bitfield_default },
- { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_BA_THRESHOLD[] = {
- { "READ_THRES", 0, 9, &umr_bitfield_default },
- { "WRITE_THRES", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_ID[] = {
- { "DEVICE_ID", 0, 7, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_VERSION[] = {
- { "MINVER", 0, 6, &umr_bitfield_default },
- { "MAJVER", 8, 14, &umr_bitfield_default },
- { "REV", 16, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_EDC_COUNTER[] = {
- { "SDMA_UCODE_BUF_DED", 0, 0, &umr_bitfield_default },
- { "SDMA_UCODE_BUF_SEC", 1, 1, &umr_bitfield_default },
- { "SDMA_RB_CMD_BUF_SED", 2, 2, &umr_bitfield_default },
- { "SDMA_IB_CMD_BUF_SED", 3, 3, &umr_bitfield_default },
- { "SDMA_UTCL1_RD_FIFO_SED", 4, 4, &umr_bitfield_default },
- { "SDMA_UTCL1_RDBST_FIFO_SED", 5, 5, &umr_bitfield_default },
- { "SDMA_DATA_LUT_FIFO_SED", 6, 6, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF0_SED", 7, 7, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF1_SED", 8, 8, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF2_SED", 9, 9, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF3_SED", 10, 10, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF4_SED", 11, 11, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF5_SED", 12, 12, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF6_SED", 13, 13, &umr_bitfield_default },
- { "SDMA_MBANK_DATA_BUF7_SED", 14, 14, &umr_bitfield_default },
- { "SDMA_SPLIT_DAT_BUF_SED", 15, 15, &umr_bitfield_default },
- { "SDMA_MC_WR_ADDR_FIFO_SED", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_EDC_COUNTER_CLEAR[] = {
- { "DUMMY", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_STATUS2_REG[] = {
- { "ID", 0, 1, &umr_bitfield_default },
- { "F32_INSTR_PTR", 2, 11, &umr_bitfield_default },
- { "CMD_OP", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_ATOMIC_CNTL[] = {
- { "LOOP_TIMER", 0, 30, &umr_bitfield_default },
- { "ATOMIC_RTN_INT_ENABLE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_ATOMIC_PREOP_LO[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_ATOMIC_PREOP_HI[] = {
- { "DATA", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_CNTL[] = {
- { "REDO_ENABLE", 0, 0, &umr_bitfield_default },
- { "REDO_DELAY", 1, 10, &umr_bitfield_default },
- { "REDO_WATERMK", 11, 13, &umr_bitfield_default },
- { "INVACK_DELAY", 14, 23, &umr_bitfield_default },
- { "REQL2_CREDIT", 24, 28, &umr_bitfield_default },
- { "VADDR_WATERMK", 29, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_WATERMK[] = {
- { "REQMC_WATERMK", 0, 9, &umr_bitfield_default },
- { "REQPG_WATERMK", 10, 17, &umr_bitfield_default },
- { "INVREQ_WATERMK", 18, 25, &umr_bitfield_default },
- { "XNACK_WATERMK", 26, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_RD_STATUS[] = {
- { "RQMC_RET_ADDR_FIFO_EMPTY", 0, 0, &umr_bitfield_default },
- { "RQMC_REQ_FIFO_EMPTY", 1, 1, &umr_bitfield_default },
- { "RTPG_RET_BUF_EMPTY", 2, 2, &umr_bitfield_default },
- { "RTPG_VADDR_FIFO_EMPTY", 3, 3, &umr_bitfield_default },
- { "RQPG_HEAD_VIRT_FIFO_EMPTY", 4, 4, &umr_bitfield_default },
- { "RQPG_REDO_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
- { "RQPG_REQPAGE_FIFO_EMPTY", 6, 6, &umr_bitfield_default },
- { "RQPG_XNACK_FIFO_EMPTY", 7, 7, &umr_bitfield_default },
- { "RQPG_INVREQ_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
- { "RQMC_RET_ADDR_FIFO_FULL", 9, 9, &umr_bitfield_default },
- { "RQMC_REQ_FIFO_FULL", 10, 10, &umr_bitfield_default },
- { "RTPG_RET_BUF_FULL", 11, 11, &umr_bitfield_default },
- { "RTPG_VADDR_FIFO_FULL", 12, 12, &umr_bitfield_default },
- { "RQPG_HEAD_VIRT_FIFO_FULL", 13, 13, &umr_bitfield_default },
- { "RQPG_REDO_FIFO_FULL", 14, 14, &umr_bitfield_default },
- { "RQPG_REQPAGE_FIFO_FULL", 15, 15, &umr_bitfield_default },
- { "RQPG_XNACK_FIFO_FULL", 16, 16, &umr_bitfield_default },
- { "RQPG_INVREQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
- { "PAGE_FAULT", 18, 18, &umr_bitfield_default },
- { "PAGE_NULL", 19, 19, &umr_bitfield_default },
- { "REQL2_IDLE", 20, 20, &umr_bitfield_default },
- { "CE_L1_STALL", 21, 21, &umr_bitfield_default },
- { "NEXT_RD_VECTOR", 22, 25, &umr_bitfield_default },
- { "MERGE_STATE", 26, 28, &umr_bitfield_default },
- { "ADDR_RD_RTR", 29, 29, &umr_bitfield_default },
- { "WPTR_POLLING", 30, 30, &umr_bitfield_default },
- { "INVREQ_SIZE", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_WR_STATUS[] = {
- { "RQMC_RET_ADDR_FIFO_EMPTY", 0, 0, &umr_bitfield_default },
- { "RQMC_REQ_FIFO_EMPTY", 1, 1, &umr_bitfield_default },
- { "RTPG_RET_BUF_EMPTY", 2, 2, &umr_bitfield_default },
- { "RTPG_VADDR_FIFO_EMPTY", 3, 3, &umr_bitfield_default },
- { "RQPG_HEAD_VIRT_FIFO_EMPTY", 4, 4, &umr_bitfield_default },
- { "RQPG_REDO_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
- { "RQPG_REQPAGE_FIFO_EMPTY", 6, 6, &umr_bitfield_default },
- { "RQPG_XNACK_FIFO_EMPTY", 7, 7, &umr_bitfield_default },
- { "RQPG_INVREQ_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
- { "RQMC_RET_ADDR_FIFO_FULL", 9, 9, &umr_bitfield_default },
- { "RQMC_REQ_FIFO_FULL", 10, 10, &umr_bitfield_default },
- { "RTPG_RET_BUF_FULL", 11, 11, &umr_bitfield_default },
- { "RTPG_VADDR_FIFO_FULL", 12, 12, &umr_bitfield_default },
- { "RQPG_HEAD_VIRT_FIFO_FULL", 13, 13, &umr_bitfield_default },
- { "RQPG_REDO_FIFO_FULL", 14, 14, &umr_bitfield_default },
- { "RQPG_REQPAGE_FIFO_FULL", 15, 15, &umr_bitfield_default },
- { "RQPG_XNACK_FIFO_FULL", 16, 16, &umr_bitfield_default },
- { "RQPG_INVREQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
- { "PAGE_FAULT", 18, 18, &umr_bitfield_default },
- { "PAGE_NULL", 19, 19, &umr_bitfield_default },
- { "REQL2_IDLE", 20, 20, &umr_bitfield_default },
- { "F32_WR_RTR", 21, 21, &umr_bitfield_default },
- { "NEXT_WR_VECTOR", 22, 24, &umr_bitfield_default },
- { "MERGE_STATE", 25, 27, &umr_bitfield_default },
- { "RPTR_DATA_FIFO_EMPTY", 28, 28, &umr_bitfield_default },
- { "RPTR_DATA_FIFO_FULL", 29, 29, &umr_bitfield_default },
- { "WRREQ_DATA_FIFO_EMPTY", 30, 30, &umr_bitfield_default },
- { "WRREQ_DATA_FIFO_FULL", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_INV0[] = {
- { "INV_MIDDLE", 0, 0, &umr_bitfield_default },
- { "RD_TIMEOUT", 1, 1, &umr_bitfield_default },
- { "WR_TIMEOUT", 2, 2, &umr_bitfield_default },
- { "RD_IN_INVADR", 3, 3, &umr_bitfield_default },
- { "WR_IN_INVADR", 4, 4, &umr_bitfield_default },
- { "PAGE_NULL_SW", 5, 5, &umr_bitfield_default },
- { "XNACK_IS_INVADR", 6, 6, &umr_bitfield_default },
- { "INVREQ_ENABLE", 7, 7, &umr_bitfield_default },
- { "NACK_TIMEOUT_SW", 8, 8, &umr_bitfield_default },
- { "NFLUSH_INV_IDLE", 9, 9, &umr_bitfield_default },
- { "FLUSH_INV_IDLE", 10, 10, &umr_bitfield_default },
- { "INV_FLUSHTYPE", 11, 11, &umr_bitfield_default },
- { "INV_VMID_VEC", 12, 27, &umr_bitfield_default },
- { "INV_ADDR_HI", 28, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_INV1[] = {
- { "INV_ADDR_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_INV2[] = {
- { "INV_NFLUSH_VMID_VEC", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_RD_XNACK0[] = {
- { "XNACK_ADDR_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_RD_XNACK1[] = {
- { "XNACK_ADDR_HI", 0, 3, &umr_bitfield_default },
- { "XNACK_VMID", 4, 7, &umr_bitfield_default },
- { "XNACK_VECTOR", 8, 25, &umr_bitfield_default },
- { "IS_XNACK", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_WR_XNACK0[] = {
- { "XNACK_ADDR_LO", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_WR_XNACK1[] = {
- { "XNACK_ADDR_HI", 0, 3, &umr_bitfield_default },
- { "XNACK_VMID", 4, 7, &umr_bitfield_default },
- { "XNACK_VECTOR", 8, 25, &umr_bitfield_default },
- { "IS_XNACK", 26, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_TIMEOUT[] = {
- { "RD_XNACK_LIMIT", 0, 15, &umr_bitfield_default },
- { "WR_XNACK_LIMIT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UTCL1_PAGE[] = {
- { "VM_HOLE", 0, 0, &umr_bitfield_default },
- { "REQ_TYPE", 1, 4, &umr_bitfield_default },
- { "USE_MTYPE", 6, 8, &umr_bitfield_default },
- { "USE_PT_SNOOP", 9, 9, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_POWER_CNTL_IDLE[] = {
- { "DELAY0", 0, 15, &umr_bitfield_default },
- { "DELAY1", 16, 23, &umr_bitfield_default },
- { "DELAY2", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RELAX_ORDERING_LUT[] = {
- { "RESERVED0", 0, 0, &umr_bitfield_default },
- { "COPY", 1, 1, &umr_bitfield_default },
- { "WRITE", 2, 2, &umr_bitfield_default },
- { "RESERVED3", 3, 3, &umr_bitfield_default },
- { "RESERVED4", 4, 4, &umr_bitfield_default },
- { "FENCE", 5, 5, &umr_bitfield_default },
- { "RESERVED76", 6, 7, &umr_bitfield_default },
- { "POLL_MEM", 8, 8, &umr_bitfield_default },
- { "COND_EXE", 9, 9, &umr_bitfield_default },
- { "ATOMIC", 10, 10, &umr_bitfield_default },
- { "CONST_FILL", 11, 11, &umr_bitfield_default },
- { "PTEPDE", 12, 12, &umr_bitfield_default },
- { "TIMESTAMP", 13, 13, &umr_bitfield_default },
- { "RESERVED", 14, 26, &umr_bitfield_default },
- { "WORLD_SWITCH", 27, 27, &umr_bitfield_default },
- { "RPTR_WRB", 28, 28, &umr_bitfield_default },
- { "WPTR_POLL", 29, 29, &umr_bitfield_default },
- { "IB_FETCH", 30, 30, &umr_bitfield_default },
- { "RB_FETCH", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CHICKEN_BITS_2[] = {
- { "F32_CMD_PROC_DELAY", 0, 3, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_STATUS3_REG[] = {
- { "CMD_OP_STATUS", 0, 15, &umr_bitfield_default },
- { "PREV_VM_CMD", 16, 19, &umr_bitfield_default },
- { "EXCEPTION_IDLE", 20, 20, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PHYSICAL_ADDR_LO[] = {
- { "D_VALID", 0, 0, &umr_bitfield_default },
- { "DIRTY", 1, 1, &umr_bitfield_default },
- { "PHY_VALID", 2, 2, &umr_bitfield_default },
- { "ADDR", 12, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PHYSICAL_ADDR_HI[] = {
- { "ADDR", 0, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PHASE2_QUANTUM[] = {
- { "UNIT", 0, 3, &umr_bitfield_default },
- { "VALUE", 8, 23, &umr_bitfield_default },
- { "PREFER", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_ERROR_LOG[] = {
- { "OVERRIDE", 0, 15, &umr_bitfield_default },
- { "STATUS", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PUB_DUMMY_REG0[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PUB_DUMMY_REG1[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PUB_DUMMY_REG2[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PUB_DUMMY_REG3[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_F32_COUNTER[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_UNBREAKABLE[] = {
- { "VALUE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PERFMON_CNTL[] = {
- { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
- { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
- { "PERF_SEL0", 2, 9, &umr_bitfield_default },
- { "PERF_ENABLE1", 10, 10, &umr_bitfield_default },
- { "PERF_CLEAR1", 11, 11, &umr_bitfield_default },
- { "PERF_SEL1", 12, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PERFCOUNTER0_RESULT[] = {
- { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PERFCOUNTER1_RESULT[] = {
- { "PERF_COUNT", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE[] = {
- { "RANGE_LOW", 0, 13, &umr_bitfield_default },
- { "RANGE_HIGH", 14, 27, &umr_bitfield_default },
- { "SELECT_RW", 28, 28, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_CRD_CNTL[] = {
- { "MC_WRREQ_CREDIT", 7, 12, &umr_bitfield_default },
- { "MC_RDREQ_CREDIT", 13, 18, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_MMHUB_TRUSTLVL[] = {
- { "SECFLAG0", 0, 2, &umr_bitfield_default },
- { "SECFLAG1", 3, 5, &umr_bitfield_default },
- { "SECFLAG2", 6, 8, &umr_bitfield_default },
- { "SECFLAG3", 9, 11, &umr_bitfield_default },
- { "SECFLAG4", 12, 14, &umr_bitfield_default },
- { "SECFLAG5", 15, 17, &umr_bitfield_default },
- { "SECFLAG6", 18, 20, &umr_bitfield_default },
- { "SECFLAG7", 21, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GPU_IOV_VIOLATION_LOG[] = {
- { "VIOLATION_STATUS", 0, 0, &umr_bitfield_default },
- { "MULTIPLE_VIOLATION_STATUS", 1, 1, &umr_bitfield_default },
- { "ADDRESS", 2, 17, &umr_bitfield_default },
- { "WRITE_OPERATION", 18, 18, &umr_bitfield_default },
- { "VF", 19, 19, &umr_bitfield_default },
- { "VFID", 20, 23, &umr_bitfield_default },
- { "INITIATOR_ID", 24, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_ULV_CNTL[] = {
- { "HYSTERESIS", 0, 4, &umr_bitfield_default },
- { "ENTER_ULV_INT", 29, 29, &umr_bitfield_default },
- { "EXIT_ULV_INT", 30, 30, &umr_bitfield_default },
- { "ULV_STATUS", 31, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_EA_DBIT_ADDR_DATA[] = {
- { "VALUE", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_EA_DBIT_ADDR_INDEX[] = {
- { "VALUE", 0, 2, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_CNTL[] = {
- { "RB_ENABLE", 0, 0, &umr_bitfield_default },
- { "RB_SIZE", 1, 6, &umr_bitfield_default },
- { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
- { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
- { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
- { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
- { "RB_PRIV", 23, 23, &umr_bitfield_default },
- { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_BASE[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_BASE_HI[] = {
- { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_RPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_WPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_CNTL[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
- { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
- { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
- { "FREQUENCY", 4, 15, &umr_bitfield_default },
- { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_CNTL[] = {
- { "IB_ENABLE", 0, 0, &umr_bitfield_default },
- { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
- { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
- { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_RPTR[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_OFFSET[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_BASE_LO[] = {
- { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_BASE_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_SIZE[] = {
- { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_SKIP_CNTL[] = {
- { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_CONTEXT_STATUS[] = {
- { "SELECTED", 0, 0, &umr_bitfield_default },
- { "IDLE", 2, 2, &umr_bitfield_default },
- { "EXPIRED", 3, 3, &umr_bitfield_default },
- { "EXCEPTION", 4, 6, &umr_bitfield_default },
- { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
- { "CTXSW_READY", 8, 8, &umr_bitfield_default },
- { "PREEMPTED", 9, 9, &umr_bitfield_default },
- { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_DOORBELL[] = {
- { "ENABLE", 28, 28, &umr_bitfield_default },
- { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_CONTEXT_CNTL[] = {
- { "RESUME_CTX", 16, 16, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_STATUS[] = {
- { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
- { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_DOORBELL_LOG[] = {
- { "BE_ERROR", 0, 0, &umr_bitfield_default },
- { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_WATERMARK[] = {
- { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
- { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_DOORBELL_OFFSET[] = {
- { "OFFSET", 2, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_CSA_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_CSA_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_IB_SUB_REMAIN[] = {
- { "SIZE", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_PREEMPT[] = {
- { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_DUMMY_REG[] = {
- { "DUMMY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_RB_AQL_CNTL[] = {
- { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
- { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
- { "PACKET_STEP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MINOR_PTR_UPDATE[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA0[] = {
- { "DATA0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA1[] = {
- { "DATA1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA2[] = {
- { "DATA2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA3[] = {
- { "DATA3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA4[] = {
- { "DATA4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA5[] = {
- { "DATA5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA6[] = {
- { "DATA6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA7[] = {
- { "DATA7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA8[] = {
- { "DATA8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_GFX_MIDCMD_CNTL[] = {
- { "DATA_VALID", 0, 0, &umr_bitfield_default },
- { "COPY_MODE", 1, 1, &umr_bitfield_default },
- { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
- { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_CNTL[] = {
- { "RB_ENABLE", 0, 0, &umr_bitfield_default },
- { "RB_SIZE", 1, 6, &umr_bitfield_default },
- { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
- { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
- { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
- { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
- { "RB_PRIV", 23, 23, &umr_bitfield_default },
- { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_BASE[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_BASE_HI[] = {
- { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_RPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_RPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_WPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_WPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_WPTR_POLL_CNTL[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
- { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
- { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
- { "FREQUENCY", 4, 15, &umr_bitfield_default },
- { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_RPTR_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_RPTR_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_IB_CNTL[] = {
- { "IB_ENABLE", 0, 0, &umr_bitfield_default },
- { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
- { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
- { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_IB_RPTR[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_IB_OFFSET[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_IB_BASE_LO[] = {
- { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_IB_BASE_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_IB_SIZE[] = {
- { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_SKIP_CNTL[] = {
- { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_CONTEXT_STATUS[] = {
- { "SELECTED", 0, 0, &umr_bitfield_default },
- { "IDLE", 2, 2, &umr_bitfield_default },
- { "EXPIRED", 3, 3, &umr_bitfield_default },
- { "EXCEPTION", 4, 6, &umr_bitfield_default },
- { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
- { "CTXSW_READY", 8, 8, &umr_bitfield_default },
- { "PREEMPTED", 9, 9, &umr_bitfield_default },
- { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_DOORBELL[] = {
- { "ENABLE", 28, 28, &umr_bitfield_default },
- { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_STATUS[] = {
- { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
- { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_DOORBELL_LOG[] = {
- { "BE_ERROR", 0, 0, &umr_bitfield_default },
- { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_WATERMARK[] = {
- { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
- { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_DOORBELL_OFFSET[] = {
- { "OFFSET", 2, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_CSA_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_CSA_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_IB_SUB_REMAIN[] = {
- { "SIZE", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_PREEMPT[] = {
- { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_DUMMY_REG[] = {
- { "DUMMY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_RB_AQL_CNTL[] = {
- { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
- { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
- { "PACKET_STEP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MINOR_PTR_UPDATE[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA0[] = {
- { "DATA0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA1[] = {
- { "DATA1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA2[] = {
- { "DATA2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA3[] = {
- { "DATA3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA4[] = {
- { "DATA4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA5[] = {
- { "DATA5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA6[] = {
- { "DATA6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA7[] = {
- { "DATA7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA8[] = {
- { "DATA8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_CNTL[] = {
- { "DATA_VALID", 0, 0, &umr_bitfield_default },
- { "COPY_MODE", 1, 1, &umr_bitfield_default },
- { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
- { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_CNTL[] = {
- { "RB_ENABLE", 0, 0, &umr_bitfield_default },
- { "RB_SIZE", 1, 6, &umr_bitfield_default },
- { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
- { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
- { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
- { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
- { "RB_PRIV", 23, 23, &umr_bitfield_default },
- { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_BASE[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_BASE_HI[] = {
- { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
- { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
- { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
- { "FREQUENCY", 4, 15, &umr_bitfield_default },
- { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_CNTL[] = {
- { "IB_ENABLE", 0, 0, &umr_bitfield_default },
- { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
- { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
- { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_RPTR[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_OFFSET[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_BASE_LO[] = {
- { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_BASE_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_SIZE[] = {
- { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_SKIP_CNTL[] = {
- { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_CONTEXT_STATUS[] = {
- { "SELECTED", 0, 0, &umr_bitfield_default },
- { "IDLE", 2, 2, &umr_bitfield_default },
- { "EXPIRED", 3, 3, &umr_bitfield_default },
- { "EXCEPTION", 4, 6, &umr_bitfield_default },
- { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
- { "CTXSW_READY", 8, 8, &umr_bitfield_default },
- { "PREEMPTED", 9, 9, &umr_bitfield_default },
- { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_DOORBELL[] = {
- { "ENABLE", 28, 28, &umr_bitfield_default },
- { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_STATUS[] = {
- { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
- { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_DOORBELL_LOG[] = {
- { "BE_ERROR", 0, 0, &umr_bitfield_default },
- { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_WATERMARK[] = {
- { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
- { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_DOORBELL_OFFSET[] = {
- { "OFFSET", 2, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_CSA_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_CSA_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_IB_SUB_REMAIN[] = {
- { "SIZE", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_PREEMPT[] = {
- { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_DUMMY_REG[] = {
- { "DUMMY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_RB_AQL_CNTL[] = {
- { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
- { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
- { "PACKET_STEP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MINOR_PTR_UPDATE[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA0[] = {
- { "DATA0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA1[] = {
- { "DATA1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA2[] = {
- { "DATA2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA3[] = {
- { "DATA3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA4[] = {
- { "DATA4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA5[] = {
- { "DATA5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA6[] = {
- { "DATA6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA7[] = {
- { "DATA7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA8[] = {
- { "DATA8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_CNTL[] = {
- { "DATA_VALID", 0, 0, &umr_bitfield_default },
- { "COPY_MODE", 1, 1, &umr_bitfield_default },
- { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
- { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_CNTL[] = {
- { "RB_ENABLE", 0, 0, &umr_bitfield_default },
- { "RB_SIZE", 1, 6, &umr_bitfield_default },
- { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
- { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
- { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
- { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
- { "RB_PRIV", 23, 23, &umr_bitfield_default },
- { "RB_VMID", 24, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_BASE[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_BASE_HI[] = {
- { "ADDR", 0, 23, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_HI[] = {
- { "OFFSET", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
- { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
- { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
- { "FREQUENCY", 4, 15, &umr_bitfield_default },
- { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_CNTL[] = {
- { "IB_ENABLE", 0, 0, &umr_bitfield_default },
- { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
- { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
- { "CMD_VMID", 16, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_RPTR[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_OFFSET[] = {
- { "OFFSET", 2, 21, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_BASE_LO[] = {
- { "ADDR", 5, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_BASE_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_SIZE[] = {
- { "SIZE", 0, 19, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_SKIP_CNTL[] = {
- { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_CONTEXT_STATUS[] = {
- { "SELECTED", 0, 0, &umr_bitfield_default },
- { "IDLE", 2, 2, &umr_bitfield_default },
- { "EXPIRED", 3, 3, &umr_bitfield_default },
- { "EXCEPTION", 4, 6, &umr_bitfield_default },
- { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
- { "CTXSW_READY", 8, 8, &umr_bitfield_default },
- { "PREEMPTED", 9, 9, &umr_bitfield_default },
- { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_DOORBELL[] = {
- { "ENABLE", 28, 28, &umr_bitfield_default },
- { "CAPTURED", 30, 30, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_STATUS[] = {
- { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
- { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_DOORBELL_LOG[] = {
- { "BE_ERROR", 0, 0, &umr_bitfield_default },
- { "DATA", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_WATERMARK[] = {
- { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
- { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_DOORBELL_OFFSET[] = {
- { "OFFSET", 2, 27, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_CSA_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_CSA_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_IB_SUB_REMAIN[] = {
- { "SIZE", 0, 13, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_PREEMPT[] = {
- { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_DUMMY_REG[] = {
- { "DUMMY", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[] = {
- { "ADDR", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[] = {
- { "ADDR", 2, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_RB_AQL_CNTL[] = {
- { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
- { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
- { "PACKET_STEP", 8, 15, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MINOR_PTR_UPDATE[] = {
- { "ENABLE", 0, 0, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA0[] = {
- { "DATA0", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA1[] = {
- { "DATA1", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA2[] = {
- { "DATA2", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA3[] = {
- { "DATA3", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA4[] = {
- { "DATA4", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA5[] = {
- { "DATA5", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA6[] = {
- { "DATA6", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA7[] = {
- { "DATA7", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA8[] = {
- { "DATA8", 0, 31, &umr_bitfield_default },
};
static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_CNTL[] = {
- { "DATA_VALID", 0, 0, &umr_bitfield_default },
- { "COPY_MODE", 1, 1, &umr_bitfield_default },
- { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
- { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
};
diff --git a/src/lib/ip/smu713_bits.i b/src/lib/ip/smu713_bits.i
index 36e01e79a35c..cd9f4e32b5e6 100644
--- a/src/lib/ip/smu713_bits.i
+++ b/src/lib/ip/smu713_bits.i
@@ -3874,6 +3874,10 @@ static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = {
{ "VBI_PREDICTION", 0, 31, &umr_bitfield_default },
};
+static struct umr_bitfield ixPWR_SVI2_STATUS[] = {
+ { "PLANE1_VID", 0, 7, &umr_bitfield_default },
+ { "PLANE2_VID", 8, 15, &umr_bitfield_default },
+};
static struct umr_bitfield ixCURRENT_PG_STATUS[] = {
{ "VCE_PG_STATUS", 1, 1, &umr_bitfield_default },
{ "UVD_PG_STATUS", 2, 2, &umr_bitfield_default },
diff --git a/src/lib/ip/smu713_regs.i b/src/lib/ip/smu713_regs.i
index 8a632b41624e..f72df0b511fe 100644
--- a/src/lib/ip/smu713_regs.i
+++ b/src/lib/ip/smu713_regs.i
@@ -886,6 +886,7 @@
{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, &ixCG_FREQ_TRAN_VOTING_6[0], sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, &ixCG_FREQ_TRAN_VOTING_7[0], sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
{ "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, &ixCG_DISPLAY_GAP_CNTL2[0], sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, 0 },
+ { "ixPWR_SVI2_STATUS", REG_SMC, 0xC0200294, &ixPWR_SVI2_STATUS[0], sizeof(ixPWR_SVI2_STATUS)/sizeof(ixPWR_SVI2_STATUS[0]), 0, 0 },
{ "ixCURRENT_PG_STATUS", REG_SMC, 0xc020029c, &ixCURRENT_PG_STATUS[0], sizeof(ixCURRENT_PG_STATUS)/sizeof(ixCURRENT_PG_STATUS[0]), 0, 0 },
{ "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, &ixLCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
{ "ixPWR_CKS_ENABLE", REG_SMC, 0xc020034c, &ixPWR_CKS_ENABLE[0], sizeof(ixPWR_CKS_ENABLE)/sizeof(ixPWR_CKS_ENABLE[0]), 0, 0 },
--
2.14.3
