On 12/23/2017 07:40 AM, Felix Kühling wrote: > As I understand it, it would require changes in the ROCr Runtime and in > the firmware (MEC microcode). It also changes the programming model, so > it may affect certain applications or higher level language runtimes > that rely on atomic operations. > How does the MEC microcode know that it is running a ROCm workload as opposed to a graphics workload that doesn't require PCIe3 atomics. Is there a specific configuration bit that is set to indicate the ROCm programming model is needed? -Tom > Regards, > Felix > > > Am 19.12.2017 um 16:04 schrieb Tom Stellard: >> Hi, >> >> How hard of a requirement is PCIe3 atomics for dGPUs with the amdkfd >> kernel driver? Is it possible to make modifications to the runtime/kernel >> driver to drop this requirement? >> >> -Tom >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >
