[Public]
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex
> Deucher
> Sent: Thursday, March 13, 2025 10:41 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Khatri, Sunil
> <Sunil.Khatri@xxxxxxx>
> Subject: [PATCH 04/11] drm/amdgpu/mes: centralize gfx_hqd mask management
>
> Move it to amdgpu_mes to align with the compute and sdma hqd masks. No
> functional change.
>
> v2: rebase on new changes
>
> Reviewed-by: Sunil Khatri<sunil.khatri@xxxxxxx>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 16 +++-------------
> drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 15 +++------------
> 3 files changed, 28 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index 6f5e272d7ded3..5abc1ca0fee98 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -108,6 +108,28 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
> adev->mes.vmid_mask_mmhub = 0xffffff00;
> adev->mes.vmid_mask_gfxhub = 0xffffff00;
>
> + for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) {
> + /* use only 1st ME pipe */
> + if (i >= adev->gfx.me.num_pipe_per_me)
> + continue;
If only requires setting the 1st pipe MES mask here, it seems unnecessary to continue the rest setting loop.
Other than that, the patch is Reviewed-by: Prike Liang <Prike.Liang@xxxxxxx>.
Thanks,
Prike
> + if (amdgpu_ip_version(adev, GC_HWIP, 0) >=
> + IP_VERSION(12, 0, 0))
> + /*
> + * GFX V12 has only one GFX pipe, but 8 queues in it.
> + * GFX pipe 0 queue 0 is being used by Kernel queue.
> + * Set GFX pipe 0 queue 1-7 for MES scheduling
> + * mask = 1111 1110b
> + */
> + adev->mes.gfx_hqd_mask[i] = 0xFE;
> + else
> + /*
> + * GFX pipe 0 queue 0 is being used by Kernel queue.
> + * Set GFX pipe 0 queue 1 for MES scheduling
> + * mask = 10b
> + */
> + adev->mes.gfx_hqd_mask[i] = 0x2;
> + }
> +
> for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
> /* use only 1st MEC pipes */
> if (i >= adev->gfx.mec.num_pipe_per_mec) diff --git
> a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index a569d09a1a748..39b45d8b5f049 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -669,18 +669,6 @@ static int mes_v11_0_misc_op(struct amdgpu_mes
> *mes,
> offsetof(union MESAPI__MISC, api_status)); }
>
> -static void mes_v11_0_set_gfx_hqd_mask(union
> MESAPI_SET_HW_RESOURCES *pkt) -{
> - /*
> - * GFX pipe 0 queue 0 is being used by Kernel queue.
> - * Set GFX pipe 0 queue 1 for MES scheduling
> - * mask = 10b
> - * GFX pipe 1 can't be used for MES due to HW limitation.
> - */
> - pkt->gfx_hqd_mask[0] = 0x2;
> - pkt->gfx_hqd_mask[1] = 0;
> -}
> -
> static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) {
> int i;
> @@ -705,7 +693,9 @@ static int mes_v11_0_set_hw_resources(struct
> amdgpu_mes *mes)
> mes_set_hw_res_pkt.compute_hqd_mask[i] =
> mes->compute_hqd_mask[i];
>
> - mes_v11_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
> + for (i = 0; i < MAX_GFX_PIPES; i++)
> + mes_set_hw_res_pkt.gfx_hqd_mask[i] =
> + mes->gfx_hqd_mask[i];
>
> for (i = 0; i < MAX_SDMA_PIPES; i++)
> mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes-
> >sdma_hqd_mask[i]; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> index 96336652d14c5..519f054bec60d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> @@ -694,17 +694,6 @@ static int mes_v12_0_set_hw_resources_1(struct
> amdgpu_mes *mes, int pipe)
> offsetof(union MESAPI_SET_HW_RESOURCES_1,
> api_status)); }
>
> -static void mes_v12_0_set_gfx_hqd_mask(union
> MESAPI_SET_HW_RESOURCES *pkt) -{
> - /*
> - * GFX V12 has only one GFX pipe, but 8 queues in it.
> - * GFX pipe 0 queue 0 is being used by Kernel queue.
> - * Set GFX pipe 0 queue 1-7 for MES scheduling
> - * mask = 1111 1110b
> - */
> - pkt->gfx_hqd_mask[0] = 0xFE;
> -}
> -
> static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) {
> int i;
> @@ -727,7 +716,9 @@ static int mes_v12_0_set_hw_resources(struct
> amdgpu_mes *mes, int pipe)
> mes_set_hw_res_pkt.compute_hqd_mask[i] =
> mes->compute_hqd_mask[i];
>
> - mes_v12_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
> + for (i = 0; i < MAX_GFX_PIPES; i++)
> + mes_set_hw_res_pkt.gfx_hqd_mask[i] =
> + mes->gfx_hqd_mask[i];
>
> for (i = 0; i < MAX_SDMA_PIPES; i++)
> mes_set_hw_res_pkt.sdma_hqd_mask[i] =
> --
> 2.48.1
