[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Asad Kamal <asad.kamal@xxxxxxx>
Thanks & Regards
Asad
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Lazar, Lijo
Sent: Tuesday, March 18, 2025 6:52 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>
Subject: Re: [PATCH 1/2] drm/amd/pm: Add debug bit for smu pool allocation
<Ping>
On 3/7/2025 11:50 AM, Lijo Lazar wrote:
> In certain cases, it's desirable to avoid PMFW log transactions to
> system memory. Add a mask bit to decide whether to allocate smu pool
> in device memory or system memory.
>
> Signed-off-by: Lijo Lazar <lijo.lazar@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++
> drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 ++-
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 5 ++++-
> 3 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index b161daa90019..22775c204632 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -140,6 +140,7 @@ enum AMDGPU_DEBUG_MASK {
> AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4),
> AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5),
> AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6),
> + AMDGPU_DEBUG_SMU_POOL = BIT(7),
> };
>
> unsigned int amdgpu_vram_limit = UINT_MAX; @@ -2231,6 +2232,10 @@
> static void amdgpu_init_debug_options(struct amdgpu_device *adev)
> pr_info("debug: ring reset disabled\n");
> adev->debug_disable_gpu_ring_reset = true;
> }
> + if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) {
> + pr_info("debug: use vram for smu pool\n");
> + adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM;
> + }
> }
>
> static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev,
> unsigned long flags) diff --git
> a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> index 9fb26b5c8ae7..f93d287dbf13 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
> @@ -295,7 +295,8 @@ enum ip_power_state { };
>
> /* Used to mask smu debug modes */
> -#define SMU_DEBUG_HALT_ON_ERROR 0x1
> +#define SMU_DEBUG_HALT_ON_ERROR BIT(0)
> +#define SMU_DEBUG_POOL_USE_VRAM BIT(1)
>
> #define MAX_SMU_I2C_BUSES 2
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 54a31d586d55..f6def50ba22d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1027,7 +1027,10 @@ static int smu_alloc_memory_pool(struct
> smu_context *smu)
>
> memory_pool->size = pool_size;
> memory_pool->align = PAGE_SIZE;
> - memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
> + memory_pool->domain =
> + (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ?
> + AMDGPU_GEM_DOMAIN_VRAM :
> + AMDGPU_GEM_DOMAIN_GTT;
>
> switch (pool_size) {
> case SMU_MEMORY_POOL_SIZE_256_MB:
