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Regards,
Prike
> -----Original Message-----
> From: Liang, Prike <Prike.Liang@xxxxxxx>
> Sent: Tuesday, December 24, 2024 2:16 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Lazar, Lijo
> <Lijo.Lazar@xxxxxxx>; Liang, Prike <Prike.Liang@xxxxxxx>
> Subject: [PATCH] drm/amdgpu: reduce RLC safe mode request for gfx clock gating
>
> The driver can only request one time for the power safe mode instead of polling and
> disabling the power feature each time prior to program the GFX clock gating control
> registers. This update will reduce the latency on the GFX clock gating entry.
>
> Signed-off-by: Prike Liang <Prike.Liang@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 ++++--------
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 ++------------
> 2 files changed, 6 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index af73f85527b7..6a025438f9d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -5639,8 +5639,6 @@ static void
> gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev {
> uint32_t temp, data;
>
> - amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
> -
> /* It is disabled by HW by default */
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
> if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { @@ -
> 5734,8 +5732,6 @@ static void
> gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
> /* 7- wait for RLC_SERDES_CU_MASTER &
> RLC_SERDES_NONCU_MASTER idle */
> gfx_v8_0_wait_for_rlc_serdes(adev);
> }
> -
> - amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> }
>
> static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device
> *adev, @@ -5745,8 +5741,6 @@ static void
> gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
>
> temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
>
> - amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
> -
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
> temp1 = data1 =
> RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
> data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
> @@ -5827,12 +5821,12 @@ static void
> gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
> }
>
> gfx_v8_0_wait_for_rlc_serdes(adev);
> -
> - amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> }
> static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> bool enable)
> {
> + amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
> +
> if (enable) {
> /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
> * === MGCG + MGLS + TS(CG/LS) ===
> @@ -5846,6 +5840,8 @@ static int gfx_v8_0_update_gfx_clock_gating(struct
> amdgpu_device *adev,
> gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
> gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
> }
> +
> + amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 4b5006dc3d34..fa572b40989e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4964,8 +4964,6 @@ static void
> gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev {
> uint32_t data, def;
>
> - amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
> -
> /* It is disabled by HW by default */
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
> /* 1 - RLC_CGTT_MGCG_OVERRIDE */
> @@ -5030,8 +5028,6 @@ static void
> gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
> WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
> }
> }
> -
> - amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> }
>
> static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, @@ -
> 5042,8 +5038,6 @@ static void gfx_v9_0_update_3d_clock_gating(struct
> amdgpu_device *adev,
> if (!adev->gfx.num_gfx_rings)
> return;
>
> - amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
> -
> /* Enable 3D CGCG/CGLS */
> if (enable) {
> /* write cmd to clear cgcg/cgls ov */ @@ -5085,8 +5079,6 @@ static
> void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
> if (def != data)
> WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D,
> data);
> }
> -
> - amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> }
>
> static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device
> *adev, @@ -5094,8 +5086,6 @@ static void
> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev {
> uint32_t def, data;
>
> - amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
> -
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
> def = data = RREG32_SOC15(GC, 0,
> mmRLC_CGTT_MGCG_OVERRIDE);
> /* unset CGCG override */
> @@ -5137,13 +5127,12 @@ static void
> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
> if (def != data)
> WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL,
> data);
> }
> -
> - amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> }
>
> static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> bool enable)
> {
> + amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
> if (enable) {
> /* CGCG/CGLS should be enabled after MGCG/MGLS
> * === MGCG + MGLS ===
> @@ -5163,6 +5152,7 @@ static int gfx_v9_0_update_gfx_clock_gating(struct
> amdgpu_device *adev,
> /* === MGCG + MGLS === */
> gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
> }
> + amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> return 0;
> }
>
> --
> 2.34.1
