Re: [PATCH 29/32] drm/amdgpu: dump_ip_state for each vcn instance

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Hello Boyuan

It probably wont work fine as memory allocated for core dump also needs to change based on ip design where not we have an ip_block for each instance too.

So here is what i think and let me know if that sounds fine with you. Once you get the review complete for patches #1 - #27 get them merged and on that code base i will rework the changes needs for core dump for vcn and then you could get rest of your changes reviewed and merged.

Also i am assuming there is no dependency of patches if they are in order and build independently so you can leave the ipdump patches #28 and #29 and let the review process complete. I need to change them according to new design and validate too.

Ignore the review on these two patches till then :)

Regards
Sunil Khatri

On 10/22/2024 2:29 PM, Khatri, Sunil wrote:

[AMD Official Use Only - AMD Internal Distribution Only]


Validate the ip dump date first for vcn before committing. I reviewed based on the code changes as it looks fine.

 

From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Khatri, Sunil
Sent: Tuesday, October 22, 2024 2:27 PM
To: Zhang, Boyuan <Boyuan.Zhang@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Liu, Leo <Leo.Liu@xxxxxxx>; Koenig, Christian <Christian.Koenig@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>
Subject: Re: [PATCH 29/32] drm/amdgpu: dump_ip_state for each vcn instance

 

Reviewed-by: Sunil Khatri <sunil.khatri@xxxxxxx>

On 10/17/2024 6:50 PM, boyuan.zhang@xxxxxxx wrote:

From: Boyuan Zhang <boyuan.zhang@xxxxxxx>
 
Perform dump_ip_state only for the instance of the current vcn IP block,
instead of perform it for all vcn instances.
 
Signed-off-by: Boyuan Zhang <boyuan.zhang@xxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 27 +++++++++----------
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c   | 27 +++++++++----------
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c   | 27 +++++++++----------
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 27 +++++++++----------
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c   | 31 +++++++++++-----------
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 35 ++++++++++++-------------
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 31 +++++++++++-----------
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 27 +++++++++----------
 8 files changed, 112 insertions(+), 120 deletions(-)
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 9255bcfc6c3d..27e0f206c9dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1964,7 +1964,8 @@ static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
 static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
 {
  struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
  bool is_powered;
  uint32_t inst_off;
  uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
@@ -1972,21 +1973,19 @@ static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
  if (!adev->vcn.ip_dump)
         return;
 
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-        if (adev->vcn.harvest_config & (1 << i))
-                continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+        return;
 
-        inst_off = i * reg_count;
-        /* mmUVD_POWER_STATUS is always readable and is first element of the array */
-        adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
-        is_powered = (adev->vcn.ip_dump[inst_off] &
-                  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
 
-        if (is_powered)
-                for (j = 1; j < reg_count; j++)
-                        adev->vcn.ip_dump[inst_off + j] =
-                          RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
- }
+ if (is_powered)
+        for (j = 1; j < reg_count; j++)
+                adev->vcn.ip_dump[inst_off + j] =
+                  RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], inst));
 }
 
 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 94f000ed4895..665b749c5ac0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -2072,7 +2072,8 @@ static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
 static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
 {
  struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
  bool is_powered;
  uint32_t inst_off;
  uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
@@ -2080,21 +2081,19 @@ static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
  if (!adev->vcn.ip_dump)
         return;
 
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-        if (adev->vcn.harvest_config & (1 << i))
-                continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+        return;
 
-        inst_off = i * reg_count;
-        /* mmUVD_POWER_STATUS is always readable and is first element of the array */
-        adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
-        is_powered = (adev->vcn.ip_dump[inst_off] &
-                  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
 
-        if (is_powered)
-                for (j = 1; j < reg_count; j++)
-                        adev->vcn.ip_dump[inst_off + j] =
-                          RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
- }
+ if (is_powered)
+        for (j = 1; j < reg_count; j++)
+                adev->vcn.ip_dump[inst_off + j] =
+                  RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], inst));
 }
 
 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 7c9a0169215e..5332b2903ce1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1946,7 +1946,8 @@ static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
 static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
 {
  struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
  bool is_powered;
  uint32_t inst_off;
  uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
@@ -1954,21 +1955,19 @@ static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
  if (!adev->vcn.ip_dump)
         return;
 
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-        if (adev->vcn.harvest_config & (1 << i))
-                continue;

Since this for loop is removed which dump for each instances,clear my understanding here, there are multiple ip_blocks for vcn now and ip_block->instance is 0, 1, 2, 3 etc representing one instance ?
Assuming the use case of 2 instances so first time when vcn_v2_5_dump_ip_state is called it will comes with ip_block->instance = 0 and then 1 and 2 in sequence as we are dumping that information in loop and storing in coredump in that sequence only. 

 
+ if (adev->vcn.harvest_config & (1 << inst))
+        return;
 
-        inst_off = i * reg_count;
-        /* mmUVD_POWER_STATUS is always readable and is first element of the array */
-        adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
-        is_powered = (adev->vcn.ip_dump[inst_off] &
-                  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
 
-        if (is_powered)
-                for (j = 1; j < reg_count; j++)
-                        adev->vcn.ip_dump[inst_off + j] =
-                          RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i));
- }
+ if (is_powered)
+        for (j = 1; j < reg_count; j++)
+                adev->vcn.ip_dump[inst_off + j] =
+                  RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], inst));
  Storage we have linear to accomodate each vcn instance. So we need to make sure that when dump is called for instance sequentially we are adding values in vcn.ip_dump in same order so print should give right value else there could be a mismatch based on existing logic. Please try to cause a dump and hack around the code so is_powered is bypassed and we dump the values for each instance thats the only way to see if its working fine.

By looking at the code it seems it should work but there are some vcn variable which i am not so sure in new design.  Also patch for dump should come first and then print to reverse the order of 28 and 29 patch.
But testing is needed to make sure its working fine.
Regards
Sunil khatri

 
 }
 
 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 061c958700d8..40a3d29d4e71 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2269,7 +2269,8 @@ static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
 static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
 {
  struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
  bool is_powered;
  uint32_t inst_off;
  uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
@@ -2277,21 +2278,19 @@ static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
  if (!adev->vcn.ip_dump)
         return;
 
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-        if (adev->vcn.harvest_config & (1 << i))
-                continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+        return;
 
-        inst_off = i * reg_count;
-        /* mmUVD_POWER_STATUS is always readable and is first element of the array */
-        adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
-        is_powered = (adev->vcn.ip_dump[inst_off] &
-                      UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+                  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
 
-        if (is_powered)
-                for (j = 1; j < reg_count; j++)
-                        adev->vcn.ip_dump[inst_off + j] =
-                          RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i));
- }
+ if (is_powered)
+        for (j = 1; j < reg_count; j++)
+                adev->vcn.ip_dump[inst_off + j] =
+                  RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], inst));
 }
 
 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index fdf346bf3e34..3b2f4f1e0939 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -2177,7 +2177,8 @@ static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
 static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
 {
  struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
  bool is_powered;
  uint32_t inst_off;
  uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
@@ -2185,22 +2186,20 @@ static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
  if (!adev->vcn.ip_dump)
         return;
 
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-        if (adev->vcn.harvest_config & (1 << i))
-                continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+        return;
 
-        inst_off = i * reg_count;
-        /* mmUVD_POWER_STATUS is always readable and is first element of the array */
-        adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
-        is_powered = (adev->vcn.ip_dump[inst_off] &
-                  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
-        if (is_powered)
-                for (j = 1; j < reg_count; j++)
-                        adev->vcn.ip_dump[inst_off + j] =
-                          RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
-                                                                 i));
- }
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+ if (is_powered)
+        for (j = 1; j < reg_count; j++)
+                adev->vcn.ip_dump[inst_off + j] =
+                  RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
+                                                         inst));
 }
 
 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index daaf2fb6b3e5..be03d31cb206 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1757,7 +1757,8 @@ static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
 static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
 {
  struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
  bool is_powered;
  uint32_t inst_off, inst_id;
  uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
@@ -1765,23 +1766,21 @@ static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
  if (!adev->vcn.ip_dump)
         return;
 
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-        if (adev->vcn.harvest_config & (1 << i))
-                continue;
-
-        inst_id = GET_INST(VCN, i);
-        inst_off = i * reg_count;
-        /* mmUVD_POWER_STATUS is always readable and is first element of the array */
-        adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
-        is_powered = (adev->vcn.ip_dump[inst_off] &
-                  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
-        if (is_powered)
-                for (j = 1; j < reg_count; j++)
-                        adev->vcn.ip_dump[inst_off + j] =
-                         RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
-                                                                 inst_id));
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+        return;
+
+ inst_id = GET_INST(VCN, inst);
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+ if (is_powered)
+        for (j = 1; j < reg_count; j++)
+                adev->vcn.ip_dump[inst_off + j] =
+                 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
+                                                         inst_id));
 }
 
 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index ff8db22b9614..43b1f3d06157 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1638,7 +1638,8 @@ static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
 static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
 {
  struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
  bool is_powered;
  uint32_t inst_off;
  uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
@@ -1646,22 +1647,20 @@ static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
  if (!adev->vcn.ip_dump)
         return;
 
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-        if (adev->vcn.harvest_config & (1 << i))
-                continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+        return;
 
-        inst_off = i * reg_count;
-        /* mmUVD_POWER_STATUS is always readable and is first element of the array */
-        adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
-        is_powered = (adev->vcn.ip_dump[inst_off] &
-                  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
-        if (is_powered)
-                for (j = 1; j < reg_count; j++)
-                        adev->vcn.ip_dump[inst_off + j] =
-                         RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
-                                                                 i));
- }
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+ if (is_powered)
+        for (j = 1; j < reg_count; j++)
+                adev->vcn.ip_dump[inst_off + j] =
+                 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
+                                                         inst));
 }
 
 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index c83a5c09f410..65554c4e86cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1365,7 +1365,8 @@ static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
 static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
 {
  struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
  bool is_powered;
  uint32_t inst_off;
  uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
@@ -1373,21 +1374,19 @@ static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
  if (!adev->vcn.ip_dump)
         return;
 
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-        if (adev->vcn.harvest_config & (1 << i))
-                continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+        return;
 
-        inst_off = i * reg_count;
-        /* mmUVD_POWER_STATUS is always readable and is first element of the array */
-        adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
-        is_powered = (adev->vcn.ip_dump[inst_off] &
-                  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
 
-        if (is_powered)
-                for (j = 1; j < reg_count; j++)
-                        adev->vcn.ip_dump[inst_off + j] =
-                          RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i));
- }
+ if (is_powered)
+        for (j = 1; j < reg_count; j++)
+                adev->vcn.ip_dump[inst_off + j] =
+                  RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], inst));
 }
 
 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
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