[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by: Tao Zhou <tao.zhou1@xxxxxxx> > -----Original Message----- > From: Chai, Thomas <YiPeng.Chai@xxxxxxx> > Sent: Tuesday, October 22, 2024 2:33 PM > To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Zhou1, Tao > <Tao.Zhou1@xxxxxxx>; Li, Candice <Candice.Li@xxxxxxx>; Wang, Yang(Kevin) > <KevinYang.Wang@xxxxxxx>; Yang, Stanley <Stanley.Yang@xxxxxxx>; Chai, > Thomas <YiPeng.Chai@xxxxxxx> > Subject: [PATCH] drm/amdgpu: Reduce redundant gpu resets on nbio v7.4 > > On nbio v7.4, ras controller interrupt and athub interrupt are generated after injecting > UE to PCIE, but gpu reset only needs to be triggered once. > > Signed-off-by: YiPeng Chai <YiPeng.Chai@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c > b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c > index 9446bf6f82c1..97782a73f4b0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c > @@ -414,8 +414,7 @@ static void > nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device > /* ras_controller_int is dedicated for nbif ras error, > * not the global interrupt for sync flood > */ > - amdgpu_ras_set_fed(adev, true); > - amdgpu_ras_reset_gpu(adev); > + amdgpu_ras_global_ras_isr(adev); > } > > amdgpu_ras_error_data_fini(&err_data); > -- > 2.34.1
