> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:38 AM > To: amd-gfx at lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 02/13] drm/amdgpu:enable mcbp for gfx9 > > set bit 21 of IB.control filed to actually enable > MCBP for SRIOV > > Change-Id: Ie5126d5be95e037087cf7167c28c61975f40d784 > Signed-off-by: Monk Liu <Monk.Liu at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index ad82ab7..0d8fb51 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -3016,6 +3016,9 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct > amdgpu_ring *ring, > > control |= ib->length_dw | (vm_id << 24); > > + if (amdgpu_sriov_vf(ring->adev) && (ib->flags & > AMDGPU_IB_FLAG_PREEMPT)) > + control |= (1 << 21); Can you add proper defines for these bits? With that fixed: Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > + > amdgpu_ring_write(ring, header); > BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ > amdgpu_ring_write(ring, > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
