> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Friday, March 24, 2017 6:38 AM > To: amd-gfx at lists.freedesktop.org > Cc: Liu, Monk > Subject: [PATCH 01/13] drm/amdgpu:imple cond_exec for gfx8 > > when MCBP enalbed for gfx8, the cond_exec must also > be implemented, otherwise there will be odds to meet > cross engine (ce and me) deadlock when WORLD switch happens. > > Change-Id: I6bdb5f91dc6e1b56dcad43741a109a6eb08cb5fa > Signed-off-by: Monk Liu <Monk.Liu at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 28 > ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 5757300..396c075 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -6499,6 +6499,32 @@ static void gfx_v8_ring_emit_cntxcntl(struct > amdgpu_ring *ring, uint32_t flags) > (flags & AMDGPU_VM_DOMAIN) ? > AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr); > } > > +static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring > *ring) > +{ > + unsigned ret; New line between stack variables can code please. > + amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); > + amdgpu_ring_write(ring, lower_32_bits(ring- > >cond_exe_gpu_addr)); > + amdgpu_ring_write(ring, upper_32_bits(ring- > >cond_exe_gpu_addr)); > + amdgpu_ring_write(ring, 0); /* discard following DWs if > *cond_exec_gpu_addr==0 */ > + ret = ring->wptr & ring->buf_mask; > + amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later > */ > + return ret; > +} > + > +static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring > *ring, unsigned offset) > +{ > + unsigned cur; Same thing here. With these fixed: Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > + BUG_ON(offset > ring->buf_mask); > + BUG_ON(ring->ring[offset] != 0x55aa55aa); > + > + cur = (ring->wptr & ring->buf_mask) - 1; > + if (likely(cur > offset)) > + ring->ring[offset] = cur - offset; > + else > + ring->ring[offset] = (ring->ring_size >> 2) - offset + cur; > +} > + > + > static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) > { > struct amdgpu_device *adev = ring->adev; > @@ -6788,6 +6814,8 @@ static const struct amdgpu_ring_funcs > gfx_v8_0_ring_funcs_gfx = { > .pad_ib = amdgpu_ring_generic_pad_ib, > .emit_switch_buffer = gfx_v8_ring_emit_sb, > .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl, > + .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec, > + .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec, > }; > > static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
