I had forgotten to squash some fixups to the original patch.
This should be the correct one.
Regards,
Andres
On 2017-06-08 06:20 PM, Andres Rodriguez wrote:
> Add a new context creation parameter to express a global context priority.
>
> The priority ranking in descending order is as follows:
> * AMDGPU_CTX_PRIORITY_HIGH_HW
> * AMDGPU_CTX_PRIORITY_HIGH_SW
> * AMDGPU_CTX_PRIORITY_NORMAL
> * AMDGPU_CTX_PRIORITY_LOW_SW
> * AMDGPU_CTX_PRIORITY_LOW_HW
>
> The driver will attempt to schedule work to the hardware according to
> the priorities. No latency or throughput guarantees are provided by
> this patch.
>
> This interface intends to service the EGL_IMG_context_priority
> extension, and vulkan equivalents.
>
> Setting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER.
>
> v2: Instead of using flags, repurpose __pad
> v3: Swap enum values of _NORMAL _HIGH for backwards compatibility
> v4: Validate usermode priority and store it
> v5: Move priority validation into amdgpu_ctx_ioctl(), headline reword
> v6: add UAPI note regarding priorities requiring CAP_SYS_ADMIN
> v7: remove ctx->priority
> v8: added AMDGPU_CTX_PRIORITY_LOW, s/CAP_SYS_ADMIN/CAP_SYS_NICE
> v9: change the priority parameter to __s32
> v10: split priorities into _SW and _HW
> v11: Allow DRM_MASTER without CAP_SYS_NICE
>
> Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
> Reviewed-by: Christian König <christian.koenig at amd.com>
> Signed-off-by: Andres Rodriguez <andresx7 at gmail.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 61 +++++++++++++++++++++++++--
> drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 5 ++-
> include/uapi/drm/amdgpu_drm.h | 10 ++++-
> 3 files changed, 70 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index a11e443..9ec85d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -11,59 +11,86 @@
> * The above copyright notice and this permission notice shall be included in
> * all copies or substantial portions of the Software.
> *
> * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> * OTHER DEALINGS IN THE SOFTWARE.
> *
> * Authors: monk liu <monk.liu at amd.com>
> */
>
> #include <drm/drmP.h>
> +#include <drm/drm_auth.h>
> #include "amdgpu.h"
>
> -static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx)
> +static int amdgpu_ctx_priority_permit(struct drm_file *filp,
> + enum amd_sched_priority priority)
> +{
> + /* NORMAL and below are accessible by everyone */
> + if (priority <= AMD_SCHED_PRIORITY_NORMAL)
> + return 0;
> +
> + if (capable(CAP_SYS_NICE))
> + return 0;
> +
> + if (drm_is_current_master(filp))
> + return 0;
> +
> + return -EACCES;
> +}
> +
> +static int amdgpu_ctx_init(struct amdgpu_device *adev,
> + enum amd_sched_priority priority,
> + struct drm_file *filp,
> + struct amdgpu_ctx *ctx)
> {
> unsigned i, j;
> int r;
>
> + if (priority < 0 || priority >= AMD_SCHED_PRIORITY_MAX)
> + return -EINVAL;
> +
> + r = amdgpu_ctx_priority_permit(filp, priority);
> + if (r)
> + return r;
> +
> memset(ctx, 0, sizeof(*ctx));
> ctx->adev = adev;
> kref_init(&ctx->refcount);
> spin_lock_init(&ctx->ring_lock);
> ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS,
> sizeof(struct dma_fence*), GFP_KERNEL);
> if (!ctx->fences)
> return -ENOMEM;
>
> for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
> ctx->rings[i].sequence = 1;
> ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
> }
>
> ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);
>
> /* create context entity for each ring */
> for (i = 0; i < adev->num_rings; i++) {
> struct amdgpu_ring *ring = adev->rings[i];
> struct amd_sched_rq *rq;
>
> - rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
> + rq = &ring->sched.sched_rq[priority];
>
> if (ring == &adev->gfx.kiq.ring)
> continue;
>
> r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
> rq, amdgpu_sched_jobs);
> if (r)
> goto failed;
> }
>
> r = amdgpu_queue_mgr_init(adev, &ctx->queue_mgr);
> if (r)
> goto failed;
>
> return 0;
> @@ -88,49 +115,52 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
> for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
> for (j = 0; j < amdgpu_sched_jobs; ++j)
> dma_fence_put(ctx->rings[i].fences[j]);
> kfree(ctx->fences);
> ctx->fences = NULL;
>
> for (i = 0; i < adev->num_rings; i++)
> amd_sched_entity_fini(&adev->rings[i]->sched,
> &ctx->rings[i].entity);
>
> amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr);
> }
>
> static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
> struct amdgpu_fpriv *fpriv,
> + struct drm_file *filp,
> + enum amd_sched_priority priority,
> uint32_t *id)
> {
> struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
> struct amdgpu_ctx *ctx;
> int r;
>
> ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
> if (!ctx)
> return -ENOMEM;
>
> mutex_lock(&mgr->lock);
> r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
> if (r < 0) {
> mutex_unlock(&mgr->lock);
> kfree(ctx);
> return r;
> }
> +
> *id = (uint32_t)r;
> - r = amdgpu_ctx_init(adev, ctx);
> + r = amdgpu_ctx_init(adev, priority, filp, ctx);
> if (r) {
> idr_remove(&mgr->ctx_handles, *id);
> *id = 0;
> kfree(ctx);
> }
> mutex_unlock(&mgr->lock);
> return r;
> }
>
> static void amdgpu_ctx_do_release(struct kref *ref)
> {
> struct amdgpu_ctx *ctx;
>
> ctx = container_of(ref, struct amdgpu_ctx, refcount);
>
> @@ -176,46 +206,69 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
> out->state.hangs = 0x0;
>
> /* determine if a GPU reset has occured since the last call */
> reset_counter = atomic_read(&adev->gpu_reset_counter);
> /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
> if (ctx->reset_counter == reset_counter)
> out->state.reset_status = AMDGPU_CTX_NO_RESET;
> else
> out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
> ctx->reset_counter = reset_counter;
>
> mutex_unlock(&mgr->lock);
> return 0;
> }
>
> +static enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
> +{
> + switch (amdgpu_priority) {
> + case AMDGPU_CTX_PRIORITY_HIGH_HW:
> + return AMD_SCHED_PRIORITY_HIGH_HW;
> + case AMDGPU_CTX_PRIORITY_HIGH_SW:
> + return AMD_SCHED_PRIORITY_HIGH_SW;
> + case AMDGPU_CTX_PRIORITY_NORMAL:
> + return AMD_SCHED_PRIORITY_NORMAL;
> + case AMDGPU_CTX_PRIORITY_LOW_SW:
> + case AMDGPU_CTX_PRIORITY_LOW_HW:
> + return AMD_SCHED_PRIORITY_LOW;
> + default:
> + WARN(1, "Invalid context priority %d\n", amdgpu_priority);
> + return AMD_SCHED_PRIORITY_NORMAL;
> + }
> +}
> +
> int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
> struct drm_file *filp)
> {
> int r;
> uint32_t id;
> + enum amd_sched_priority priority;
>
> union drm_amdgpu_ctx *args = data;
> struct amdgpu_device *adev = dev->dev_private;
> struct amdgpu_fpriv *fpriv = filp->driver_priv;
>
> r = 0;
> id = args->in.ctx_id;
> + priority = amdgpu_to_sched_priority(args->in.priority);
> +
> + if (priority >= AMD_SCHED_PRIORITY_MAX)
> + return -EINVAL;
>
> switch (args->in.op) {
> case AMDGPU_CTX_OP_ALLOC_CTX:
> - r = amdgpu_ctx_alloc(adev, fpriv, &id);
> + r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id);
> args->out.alloc.ctx_id = id;
> break;
> case AMDGPU_CTX_OP_FREE_CTX:
> r = amdgpu_ctx_free(fpriv, id);
> break;
> case AMDGPU_CTX_OP_QUERY_STATE:
> r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
> break;
> default:
> return -EINVAL;
> }
>
> return r;
> }
>
> diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
> index f9d8f28..38e622c 100644
> --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
> +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
> @@ -103,31 +103,34 @@ static inline bool amd_sched_invalidate_job(struct amd_sched_job *s_job, int thr
> }
>
> /**
> * Define the backend operations called by the scheduler,
> * these functions should be implemented in driver side
> */
> struct amd_sched_backend_ops {
> struct dma_fence *(*dependency)(struct amd_sched_job *sched_job);
> struct dma_fence *(*run_job)(struct amd_sched_job *sched_job);
> void (*timedout_job)(struct amd_sched_job *sched_job);
> void (*free_job)(struct amd_sched_job *sched_job);
> };
>
> enum amd_sched_priority {
> AMD_SCHED_PRIORITY_MIN,
> - AMD_SCHED_PRIORITY_NORMAL = AMD_SCHED_PRIORITY_MIN,
> + AMD_SCHED_PRIORITY_LOW = AMD_SCHED_PRIORITY_MIN,
> + AMD_SCHED_PRIORITY_NORMAL,
> + AMD_SCHED_PRIORITY_HIGH_SW,
> + AMD_SCHED_PRIORITY_HIGH_HW,
> AMD_SCHED_PRIORITY_KERNEL,
> AMD_SCHED_PRIORITY_MAX
> };
>
> /**
> * One scheduler is implemented for each hardware ring
> */
> struct amd_gpu_scheduler {
> const struct amd_sched_backend_ops *ops;
> uint32_t hw_submission_limit;
> long timeout;
> const char *name;
> struct amd_sched_rq sched_rq[AMD_SCHED_PRIORITY_MAX];
> wait_queue_head_t wake_up_worker;
> wait_queue_head_t job_scheduled;
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 34128f6..590fc2a 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -150,37 +150,45 @@ union drm_amdgpu_bo_list {
>
> /* context related */
> #define AMDGPU_CTX_OP_ALLOC_CTX 1
> #define AMDGPU_CTX_OP_FREE_CTX 2
> #define AMDGPU_CTX_OP_QUERY_STATE 3
>
> /* GPU reset status */
> #define AMDGPU_CTX_NO_RESET 0
> /* this the context caused it */
> #define AMDGPU_CTX_GUILTY_RESET 1
> /* some other context caused it */
> #define AMDGPU_CTX_INNOCENT_RESET 2
> /* unknown cause */
> #define AMDGPU_CTX_UNKNOWN_RESET 3
>
> +/* Context priority level */
> +#define AMDGPU_CTX_PRIORITY_LOW_HW -1023
> +#define AMDGPU_CTX_PRIORITY_LOW_SW -512
> +#define AMDGPU_CTX_PRIORITY_NORMAL 0
> +/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
> +#define AMDGPU_CTX_PRIORITY_HIGH_SW 512
> +#define AMDGPU_CTX_PRIORITY_HIGH_HW 1023
> +
> struct drm_amdgpu_ctx_in {
> /** AMDGPU_CTX_OP_* */
> __u32 op;
> /** For future use, no flags defined so far */
> __u32 flags;
> __u32 ctx_id;
> - __u32 _pad;
> + __s32 priority;
> };
>
> union drm_amdgpu_ctx_out {
> struct {
> __u32 ctx_id;
> __u32 _pad;
> } alloc;
>
> struct {
> /** For future use, no flags defined so far */
> __u64 flags;
> /** Number of resets caused by this context so far. */
> __u32 hangs;
> /** Reset status since the last call of the ioctl. */
> __u32 reset_status;
