> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Wednesday, July 19, 2017 5:29 AM > To: amd-gfx at lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH] drm/amd/powerplay: add support for 3DP 4K at 120Hz on > vega10. > > Change-Id: Ic884366431afde180f9926963871a8daddc4588e > Signed-off-by: Rex Zhu <Rex.Zhu at amd.com> Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > .../amd/powerplay/hwmgr/vega10_processpptables.c | 39 > ++++++++++++++++++++-- > 1 file changed, 37 insertions(+), 2 deletions(-) > > diff --git > a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c > index 1623644..22ebecf 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c > @@ -31,6 +31,8 @@ > #include "cgs_common.h" > #include "vega10_pptable.h" > > +#define NUM_DSPCLK_LEVELS 8 > + > static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, > enum phm_platform_caps cap) > { > @@ -651,15 +653,43 @@ static int get_dcefclk_voltage_dependency_table( > const ATOM_Vega10_DCEFCLK_Dependency_Table > *clk_dep_table) > { > uint32_t table_size, i; > + uint8_t num_entries; > struct phm_ppt_v1_clock_voltage_dependency_table > *clk_table; > + struct cgs_system_info sys_info = {0}; > + uint32_t dev_id; > + uint32_t rev_id; > > PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), > "Invalid PowerPlay Table!", return -1); > > +/* > + * workaround needed to add another DPM level for pioneer cards > + * as VBIOS is locked down. > + * This DPM level was added to support 3DPM monitors @ 4K120Hz > + * > + */ > + sys_info.size = sizeof(struct cgs_system_info); > + sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV; > + cgs_query_system_info(hwmgr->device, &sys_info); > + dev_id = (uint32_t)sys_info.value; > + > + sys_info.size = sizeof(struct cgs_system_info); > + sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV; > + cgs_query_system_info(hwmgr->device, &sys_info); > + rev_id = (uint32_t)sys_info.value; > + > + if (dev_id == 0x6863 && rev_id == 0 && > + clk_dep_table->entries[clk_dep_table->ucNumEntries - > 1].ulClk < 90000) > + num_entries = clk_dep_table->ucNumEntries + 1 > > NUM_DSPCLK_LEVELS ? > + NUM_DSPCLK_LEVELS : clk_dep_table- > >ucNumEntries + 1; > + else > + num_entries = clk_dep_table->ucNumEntries; > + > + > table_size = sizeof(uint32_t) + > > sizeof(phm_ppt_v1_clock_voltage_dependency_record) * > - clk_dep_table->ucNumEntries; > + num_entries; > > clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *) > kzalloc(table_size, GFP_KERNEL); > @@ -667,7 +697,7 @@ static int get_dcefclk_voltage_dependency_table( > if (!clk_table) > return -ENOMEM; > > - clk_table->count = clk_dep_table->ucNumEntries; > + clk_table->count = (uint32_t)num_entries; > > for (i = 0; i < clk_table->count; i++) { > clk_table->entries[i].vddInd = > @@ -676,6 +706,11 @@ static int get_dcefclk_voltage_dependency_table( > le32_to_cpu(clk_dep_table- > >entries[i].ulClk); > } > > + if (i < num_entries) { > + clk_table->entries[i].vddInd = clk_dep_table->entries[i- > 1].ucVddInd; > + clk_table->entries[i].clk = 90000; > + } > + > *pp_vega10_clk_dep_table = clk_table; > > return 0; > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
