> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Emily Deng > Sent: Tuesday, July 18, 2017 11:44 PM > To: amd-gfx at lists.freedesktop.org > Cc: Deng, Emily > Subject: [PATCH v2] drm/amdgpu/gmc8: SRIOV need to program fb location > > SRIOV won't do vbios post in guest OS, and the mmMC_VM_FB_LOCATION > is pf and vf copy, so still need to program fb location for SRIOV. > > v2: No need to stop mc, and update gmc_v8_0_vram_gtt_location as well. > > BUG: SWDEV-126629 > > Signed-off-by: Emily Deng <Emily.Deng at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > index a21ea4c..a09c95b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > @@ -396,7 +396,9 @@ static int > gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) > static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, > struct amdgpu_mc *mc) > { > - u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; > + u64 base = 0; New line after the stack variables. Also, if you want the memory layout consistent between bare metal and sr-iov, you should set the base to 0xf400 so when you shift below you'll get the proper byte address (0xf400000000). That said, 0 should work fine as well. Up to you. With the new line added, feel free to add my: Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > + if (!amdgpu_sriov_vf(adev)) > + base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; > base <<= 24; > > if (mc->mc_vram_size > 0xFFC0000000ULL) { > @@ -442,6 +444,17 @@ static void gmc_v8_0_mc_program(struct > amdgpu_device *adev) > adev->mc.vram_end >> 12); > WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, > adev->vram_scratch.gpu_addr >> 12); > + > + if (amdgpu_sriov_vf(adev)) { > + tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; > + tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); > + WREG32(mmMC_VM_FB_LOCATION, tmp); > + /* XXX double check these! */ > + WREG32(mmHDP_NONSURFACE_BASE, (adev- > >mc.vram_start >> 8)); > + WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); > + WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); > + } > + > WREG32(mmMC_VM_AGP_BASE, 0); > WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); > WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
