[PATCH] drm/amd/powerplay: avoid out of bounds access on array ps.

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Am 15.11.2016 um 08:10 schrieb Rex Zhu:
> check array index first and then visit the array.
>
> Change-Id: If0c10e178fd4e4c101a733689e9a1984aaacfe3c
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com>.

> ---
>   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index b1c7751..6091b48 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -2991,19 +2991,19 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
>   	if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
>   		data->highest_mclk = memory_clock;
>   
> -	performance_level = &(ps->performance_levels
> -			[ps->performance_level_count++]);
> -
>   	PP_ASSERT_WITH_CODE(
>   			(ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
>   			"Performance levels exceeds SMC limit!",
>   			return -EINVAL);
>   
>   	PP_ASSERT_WITH_CODE(
> -			(ps->performance_level_count <=
> +			(ps->performance_level_count <
>   					hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
> -			"Performance levels exceeds Driver limit!",
> -			return -EINVAL);
> +			"Performance levels exceeds Driver limit, Skip!",
> +			return 0);
> +
> +	performance_level = &(ps->performance_levels
> +			[ps->performance_level_count++]);
>   
>   	/* Performance levels are arranged from low to high. */
>   	performance_level->memory_clock = memory_clock;




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