> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Huang Rui > Sent: Tuesday, August 30, 2016 7:50 AM > To: amd-gfx at lists.freedesktop.org; Deucher, Alexander > Cc: Wang, Ken; Yu, Hui; Huang, Ray; Huan, Alvin > Subject: [PATCH 10/14] drm/amdgpu: add rv770_get_memory_type to set > the GDDR5 flag > > Add rv770_get_memory_type to set mem_gddr5 flag, because it will be > used on the whole si dpm part. > > Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5 > Signed-off-by: Huang Rui <ray.huang at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c > b/drivers/gpu/drm/amd/amdgpu/si_dpm.c > index 5f1e5fe..563aeea 100644 > --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c > +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c > @@ -6433,8 +6433,24 @@ static void si_set_pcie_lane_width_in_smc(struct > amdgpu_device *adev, > } > } > > +void rv770_get_memory_type(struct amdgpu_device *adev) adev->mc.vram_type should be set in the gmc module. Use that instead of pi->mem_gddr5. See ci_dpm.c for example. Alex > +{ > + struct rv7xx_power_info *pi = rv770_get_pi(adev); > + u32 tmp; > + > + tmp = RREG32(MC_SEQ_MISC0); > + > + if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> > MC_SEQ_MISC0_GDDR5_SHIFT) == > + MC_SEQ_MISC0_GDDR5_VALUE) > + pi->mem_gddr5 = true; > + else > + pi->mem_gddr5 = false; > + > +} > + > static void si_dpm_setup_asic(struct amdgpu_device *adev) > { > + rv770_get_memory_type(adev); > si_read_clock_registers(adev); > si_enable_acpi_power_management(adev); > } > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
