Add rv770_get_memory_type to set mem_gddr5 flag, because it will be
used on the whole si dpm part.
Change-Id: I60f7ef38775c3b27e475f38f939905483fbb56f5
Signed-off-by: Huang Rui <ray.huang at amd.com>
---
drivers/gpu/drm/amd/amdgpu/si_dpm.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 5f1e5fe..563aeea 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -6433,8 +6433,24 @@ static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
}
}
+void rv770_get_memory_type(struct amdgpu_device *adev)
+{
+ struct rv7xx_power_info *pi = rv770_get_pi(adev);
+ u32 tmp;
+
+ tmp = RREG32(MC_SEQ_MISC0);
+
+ if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
+ MC_SEQ_MISC0_GDDR5_VALUE)
+ pi->mem_gddr5 = true;
+ else
+ pi->mem_gddr5 = false;
+
+}
+
static void si_dpm_setup_asic(struct amdgpu_device *adev)
{
+ rv770_get_memory_type(adev);
si_read_clock_registers(adev);
si_enable_acpi_power_management(adev);
}
--
2.7.4
