[PATCH 13/13] drm/amdgpu: Set ip_blocks according variable amdgpu_virtual_display.

[Emily.Deng@xxxxxxx (Emily Deng)]

For virtual display feature, if user set the option "amdgpu.virtual_display=1"
when load amdgpu.ko. Then need to set the ip_blocks with virtual display ip
blocks. And when enable virtual display, the amdgpu_dal need to be set to zero.

Signed-off-by: Emily Deng <Emily.Deng at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +
 drivers/gpu/drm/amd/amdgpu/cik.c           | 104 ++++++++++++++--------
 drivers/gpu/drm/amd/amdgpu/vi.c            | 134 ++++++++++++++++++-----------
 3 files changed, 153 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2d7eb34..008e6a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1186,6 +1186,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
 {
 	int i, r;
 
+	DRM_INFO("virtual display enabled:%d\n", amdgpu_virtual_display);
+
 	switch (adev->asic_type) {
 	case CHIP_TOPAZ:
 	case CHIP_TONGA:
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index d0442a9..4b48bcd 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2464,55 +2464,85 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks_vd[] =
 
 int cik_set_ip_blocks(struct amdgpu_device *adev)
 {
-	switch (adev->asic_type) {
-	case CHIP_BONAIRE:
+	if (amdgpu_virtual_display) {
+		amdgpu_dal = 0;
+		adev->mode_info.vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
+		switch (adev->asic_type) {
+		case CHIP_BONAIRE:
+			adev->ip_blocks = bonaire_ip_blocks_vd;
+			adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_vd);
+			break;
+		case CHIP_HAWAII:
+			adev->ip_blocks = hawaii_ip_blocks_vd;
+			adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_vd);
+			break;
+		case CHIP_KAVERI:
+			adev->ip_blocks = kaveri_ip_blocks_vd;
+			adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks_vd);
+			break;
+		case CHIP_KABINI:
+			adev->ip_blocks = kabini_ip_blocks_vd;
+			adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks_vd);
+			break;
+		case CHIP_MULLINS:
+			adev->ip_blocks = mullins_ip_blocks_vd;
+			adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks_vd);
+			break;
+		default:
+			/* FIXME: not supported yet */
+			return -EINVAL;
+		}
+	} else {
+		switch (adev->asic_type) {
+		case CHIP_BONAIRE:
 #if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-		if (amdgpu_device_has_dal_support(adev)) {
-			adev->ip_blocks = bonaire_ip_blocks_dal;
-			adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_dal);
-		} else {
+			if (amdgpu_device_has_dal_support(adev)) {
+				adev->ip_blocks = bonaire_ip_blocks_dal;
+				adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_dal);
+			} else {
+				adev->ip_blocks = bonaire_ip_blocks;
+				adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
+			}
+#else
 			adev->ip_blocks = bonaire_ip_blocks;
 			adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
-		}
-#else
-		adev->ip_blocks = bonaire_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
 #endif
-		break;
-	case CHIP_HAWAII:
+			break;
+		case CHIP_HAWAII:
 #if defined(CONFIG_DRM_AMD_DAL_DCE8_0)
-		if (amdgpu_device_has_dal_support(adev)) {
-			adev->ip_blocks = hawaii_ip_blocks_dal;
-			adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_dal);
-		} else {
+			if (amdgpu_device_has_dal_support(adev)) {
+				adev->ip_blocks = hawaii_ip_blocks_dal;
+				adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_dal);
+			} else {
+				adev->ip_blocks = hawaii_ip_blocks;
+				adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
+			}
+#else
 			adev->ip_blocks = hawaii_ip_blocks;
 			adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
-		}
-#else
-		adev->ip_blocks = hawaii_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
 #endif
-		break;
-	case CHIP_KAVERI:
-		adev->ip_blocks = kaveri_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks);
-		break;
-	case CHIP_KABINI:
-		adev->ip_blocks = kabini_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks);
-		break;
-	case CHIP_MULLINS:
-		adev->ip_blocks = mullins_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks);
-		break;
-	default:
-		/* FIXME: not supported yet */
-		return -EINVAL;
+			break;
+		case CHIP_KAVERI:
+			adev->ip_blocks = kaveri_ip_blocks;
+			adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks);
+			break;
+		case CHIP_KABINI:
+			adev->ip_blocks = kabini_ip_blocks;
+			adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks);
+			break;
+		case CHIP_MULLINS:
+			adev->ip_blocks = mullins_ip_blocks;
+			adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks);
+			break;
+		default:
+			/* FIXME: not supported yet */
+			return -EINVAL;
+		}
 	}
-
 	return 0;
 }
 
+
 static const struct amdgpu_asic_funcs cik_asic_funcs =
 {
 	.read_disabled_bios = &cik_read_disabled_bios,
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index eecc92f..432a01c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1676,77 +1676,111 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks_dal[] =
 
 int vi_set_ip_blocks(struct amdgpu_device *adev)
 {
-	switch (adev->asic_type) {
-	case CHIP_TOPAZ:
-		adev->ip_blocks = topaz_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
-		break;
-	case CHIP_FIJI:
+	if (amdgpu_virtual_display) {
+		amdgpu_dal = 0;
+		adev->mode_info.vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
+		switch (adev->asic_type) {
+		case CHIP_TOPAZ:
+			adev->ip_blocks = topaz_ip_blocks;
+			adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
+			break;
+		case CHIP_FIJI:
+			adev->ip_blocks = fiji_ip_blocks_vd;
+			adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_vd);
+			break;
+		case CHIP_TONGA:
+			adev->ip_blocks = tonga_ip_blocks_vd;
+			adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_vd);
+			break;
+		case CHIP_POLARIS11:
+		case CHIP_POLARIS10:
+			adev->ip_blocks = polaris11_ip_blocks_vd;
+			adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_vd);
+			break;
+
+		case CHIP_CARRIZO:
+		case CHIP_STONEY:
+			adev->ip_blocks = cz_ip_blocks_vd;
+			adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_vd);
+			break;
+		default:
+			/* FIXME: not supported yet */
+			return -EINVAL;
+		}
+	} else {
+		switch (adev->asic_type) {
+		case CHIP_TOPAZ:
+			adev->ip_blocks = topaz_ip_blocks;
+			adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
+			break;
+		case CHIP_FIJI:
 #if defined(CONFIG_DRM_AMD_DAL)
-		if (amdgpu_device_has_dal_support(adev)) {
-			adev->ip_blocks = fiji_ip_blocks_dal;
-			adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_dal);
-		} else {
+			if (amdgpu_device_has_dal_support(adev)) {
+				adev->ip_blocks = fiji_ip_blocks_dal;
+				adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_dal);
+			} else {
+				adev->ip_blocks = fiji_ip_blocks;
+				adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
+			}
+#else
 			adev->ip_blocks = fiji_ip_blocks;
 			adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
-		}
-#else
-		adev->ip_blocks = fiji_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
 #endif
-		break;
-	case CHIP_TONGA:
+			break;
+		case CHIP_TONGA:
 #if defined(CONFIG_DRM_AMD_DAL)
-		if (amdgpu_device_has_dal_support(adev)) {
-			adev->ip_blocks = tonga_ip_blocks_dal;
-			adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_dal);
-		} else {
+			if (amdgpu_device_has_dal_support(adev)) {
+				adev->ip_blocks = tonga_ip_blocks_dal;
+				adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_dal);
+			} else {
+				adev->ip_blocks = tonga_ip_blocks;
+				adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
+			}
+#else
 			adev->ip_blocks = tonga_ip_blocks;
 			adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
-		}
-#else
-		adev->ip_blocks = tonga_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
 #endif
-		break;
-	case CHIP_POLARIS11:
-	case CHIP_POLARIS10:
+			break;
+		case CHIP_POLARIS11:
+		case CHIP_POLARIS10:
 #if defined(CONFIG_DRM_AMD_DAL)
-		if (amdgpu_device_has_dal_support(adev)) {
-			adev->ip_blocks = polaris11_ip_blocks_dal;
-			adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_dal);
-		} else {
+			if (amdgpu_device_has_dal_support(adev)) {
+				adev->ip_blocks = polaris11_ip_blocks_dal;
+				adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_dal);
+			} else {
+				adev->ip_blocks = polaris11_ip_blocks;
+				adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
+			}
+#else
 			adev->ip_blocks = polaris11_ip_blocks;
 			adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
-		}
-#else
-		adev->ip_blocks = polaris11_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
 #endif
-		break;
-	case CHIP_CARRIZO:
-	case CHIP_STONEY:
+			break;
+		case CHIP_CARRIZO:
+		case CHIP_STONEY:
 #if defined(CONFIG_DRM_AMD_DAL)
-		if (amdgpu_device_has_dal_support(adev)) {
-			adev->ip_blocks = cz_ip_blocks_dal;
-			adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_dal);
-		} else {
+			if (amdgpu_device_has_dal_support(adev)) {
+				adev->ip_blocks = cz_ip_blocks_dal;
+				adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_dal);
+			} else {
+				adev->ip_blocks = cz_ip_blocks;
+				adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
+			}
+#else
 			adev->ip_blocks = cz_ip_blocks;
 			adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
-		}
-#else
-		adev->ip_blocks = cz_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
 #endif
-		break;
-	default:
-		/* FIXME: not supported yet */
-		return -EINVAL;
+			break;
+		default:
+			/* FIXME: not supported yet */
+			return -EINVAL;
+		}
 	}
 
 	return 0;
 }
 
+
 #define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
 #define ATI_REV_ID_FUSE_MACRO__SHIFT        9
 #define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
-- 
1.9.1