FIFO combining mode allows the separate FIFOs for multiple data channels to be used as a single FIFO for either software accesses or a single data channel or both. FIFO combined mode is described in chapter 13.10.3.5.4 from i.MX8MQ reference manual [1]. For each direction (RX/TX) fifo combine mode is read from fsl,fcomb-mode DT property. By default, if no property is specified fifo combine mode is disabled. [1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdf Signed-off-by: Daniel Baluta <daniel.baluta@xxxxxxx> --- sound/soc/fsl/fsl_sai.c | 37 +++++++++++++++++++++++++++++++++++++ sound/soc/fsl/fsl_sai.h | 9 +++++++++ 2 files changed, 46 insertions(+) diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index d0fa02188b7c..140014901fce 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -475,6 +475,35 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, } } + switch (sai->soc_data->fcomb_mode[tx]) { + case FSL_SAI_FCOMB_NONE: + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), + FSL_SAI_CR4_FCOMB_SOFT | + FSL_SAI_CR4_FCOMB_SHIFT, 0); + break; + case FSL_SAI_FCOMB_SHIFT: + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), + FSL_SAI_CR4_FCOMB_SOFT | + FSL_SAI_CR4_FCOMB_SHIFT, + FSL_SAI_CR4_FCOMB_SHIFT); + break; + case FSL_SAI_FCOMB_SOFT: + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), + FSL_SAI_CR4_FCOMB_SOFT | + FSL_SAI_CR4_FCOMB_SHIFT, + FSL_SAI_CR4_FCOMB_SOFT); + break; + case FSL_SAI_FCOMB_BOTH: + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), + FSL_SAI_CR4_FCOMB_SOFT | + FSL_SAI_CR4_FCOMB_SHIFT, + FSL_SAI_CR4_FCOMB_SOFT | + FSL_SAI_CR4_FCOMB_SHIFT); + break; + default: + break; + } + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, val_cr4); @@ -887,6 +916,14 @@ static int fsl_sai_probe(struct platform_device *pdev) } } + /* FIFO combine mode for TX/RX, defaults to disabled */ + sai->fcomb_mode[RX] = FSL_SAI_FCOMB_NONE; + sai->fcomb_mode[TX] = FSL_SAI_FCOMB_NONE; + of_property_read_u32_index(np, "fsl,fcomb-mode", RX, + &sai->fcomb_mode[RX]); + of_property_read_u32_index(np, "fsl,fcomb-mode", TX, + &sai->fcomb_mode[TX]); + /* active data lines mask for TX/RX, defaults to 1 (only the first * data line is enabled */ diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 6d32f0950ec5..abf140951187 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -115,6 +115,8 @@ #define FSL_SAI_CR3_WDFL_MASK 0x1f /* SAI Transmit and Receive Configuration 4 Register */ +#define FSL_SAI_CR4_FCOMB_SHIFT BIT(26) +#define FSL_SAI_CR4_FCOMB_SOFT BIT(27) #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) @@ -155,6 +157,12 @@ #define FSL_SAI_MAXBURST_TX 6 #define FSL_SAI_MAXBURST_RX 6 +/* FIFO combine modes */ +#define FSL_SAI_FCOMB_NONE 0 +#define FSL_SAI_FCOMB_SHIFT 1 +#define FSL_SAI_FCOMB_SOFT 2 +#define FSL_SAI_FCOMB_BOTH 3 + struct fsl_sai_soc_data { bool use_imx_pcm; unsigned int fifo_depth; @@ -177,6 +185,7 @@ struct fsl_sai { unsigned int slot_width; unsigned int dl_mask[2]; + unsigned int fcomb_mode[2]; const struct fsl_sai_soc_data *soc_data; struct snd_dmaengine_dai_dma_data dma_params_rx; -- 2.17.1 _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx https://mailman.alsa-project.org/mailman/listinfo/alsa-devel
