On Mon, Dec 18, 2017 at 07:32:41PM +0800, chen liu wrote:
> 2017-12-18 17:31 GMT+08:00 Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx>:
>
> > On Fri, Dec 15, 2017 at 09:07:15PM +0800, chen liu wrote:
> > > 2017-12-15 0:19 GMT+08:00 Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx
> > >:
> > > > On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote:
> According to your detailed description above, I understand what you mean.
> For the 'wm8960_configure_pll' function,it deduces a reasonable PLL output
> clock frequency based on the 'freq_in' frequency,the sample rate,and the bit
> clock.
>
> static int wm8960_configure_clocking(struct snd_soc_codec*codec)
> ...
> freq_out = wm8960_configure_pll(codec, freq_in, &i, &j, &k);
> if (freq_out < 0) {
> dev_err(codec->dev, "failed to configure clock via PLL\n");
> return freq_out;
> }
> wm8960_set_pll(codec, freq_in, freq_out);
> ...
>
> In the 'wm8960_configure_clocking' function, it sets the PLL divider by
> calling
> the 'wm8960_set_pll' function after calling the 'wm8960_configure_pll'.
> However,there is no support for SYSCLK_DIV = 2 in the 'wm8960_set_pll'
> function.
>
> Looking forward to your reply.
Indeed yes, as it looks like the intention was you would set the
SYSCLKDIV manually if setting the PLL manually. But why not just
call wm8960_set_pll will WM8960_SYSCLK_AUTO, and then your code
will use the configure_pll stuff?
I would like to understand what about that approach isn't working
for you as that seems like the easiest solution.
Thanks,
Charles
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