Am Donnerstag, 14. Oktober 2010, 18:11:23 schrieb Daniel Mack: > On Thu, Oct 14, 2010 at 05:54:35PM +0200, Julian Scheel wrote: > > Am Donnerstag, 14. Oktober 2010, 17:39:13 schrieb Daniel Mack: > > > What about the voltage levels? Are they within the specs? I had a quick > > > look and it seems that Vdd on the codec has to be within 3.0 .. 3.6V, > > > while the signals you provide rather seem to be in the range of 5V? The > > > absolute maximum ratings say that Vdd must not be greater than 4.0V. > > > > This might indeed be an issue. The clock signals have about 5V level... > > The data coming from the uC still has 4.2V > > This might be too much... Stays the question how to lower the voltage > > properly there... Any suggestions? > > This get more and more off-topic for the ALSA community, but ... Indeed sorry for that... > For the signals, use a voltage shifter, something like the 74LVC2T45. > For Vdd, if you have to provide that to the board, use a proper > switching power regulator with low ripple, or an LDO, and care well for > blocking. Even found an easier way, at least for the clock signals. As they are generated from a 74HCT4060 right now they are 5V. Replacing it with a 74HC4060 (or 4040) will allow me to reduce Vcc to 3V, so that the output will match. Thanks anyway... > Also check whether the voltages you applied all the time could have > damaged the chip permanently. Will check it... Have another board in backup for the worst case. Thanks so far... (c: Julian _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
