On Fri, Aug 6, 2010 at 1:25 PM, Jassi Brar <jassisinghbrar@xxxxxxxxx> wrote: > On Fri, Aug 6, 2010 at 9:36 AM, Seungwhan Youn <sw.youn@xxxxxxxxxxx> wrote: >> This patch fix to support BCLK and LRCLK rates setting as >> wm8580 Master mode. After apply this patch, LRCLK and BCLK >> signal appears correctly from wm8580 in some freq., 8kHz >> and 11.025kHz, on SMDK board. >> >> Signed-off-by: Seungwhan Youn <sw.youn@xxxxxxxxxxx> >> --- >> sound/soc/s3c24xx/smdk64xx_wm8580.c | 4 ++-- >> 1 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/sound/soc/s3c24xx/smdk64xx_wm8580.c b/sound/soc/s3c24xx/smdk64xx_wm8580.c >> index 39bb701..f3dbdfb 100644 >> --- a/sound/soc/s3c24xx/smdk64xx_wm8580.c >> +++ b/sound/soc/s3c24xx/smdk64xx_wm8580.c >> @@ -124,11 +124,11 @@ static int smdk64xx_hw_params(struct snd_pcm_substream *substream, >> if (ret < 0) >> return ret; >> >> - ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_BCLK, bfs); >> + ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_BCLK_RATE, bfs); >> if (ret < 0) >> return ret; >> >> - ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_RCLK, rfs); >> + ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_LRCLK_RATE, rfs); >> if (ret < 0) >> return ret; > > http://mailman.alsa-project.org/pipermail/alsa-devel/2009-September/021005.html > is what I meant a few days ago when I said it should be done properly. I see, if Mark's opinion is same as before, I think I can try to make another patch for it. :) > > Also, I am not sure if we can do without setting RFS,BFS on CPU side > even in slave mode. We need to confirm. > Okay, I agree to confirm this at the H/W design point of view. Thanks, Claude _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
