On Thu, 2010-05-20 at 17:53 -0500, Jorge Eduardo Candelaria wrote: > When using MCLK is configured for 19.2 Mhz, clock slicer should be > enabled and HPPLL should be bypassed in clock path. > > Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@xxxxxx> > Signed-off-by: Margarita Olaya Cabrera <magi.olaya@xxxxxx> > --- Applied. Thanks Liam -- Freelance Developer, SlimLogic Ltd ASoC and Voltage Regulator Maintainer. http://www.slimlogic.co.uk _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
