When using MCLK is configured for 19.2 Mhz, clock slicer should be enabled and HPPLL should be bypassed in clock path. Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@xxxxxx> Signed-off-by: Margarita Olaya Cabrera <magi.olaya@xxxxxx> --- sound/soc/codecs/twl6040.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index af36346..85dd4fb 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -928,7 +928,7 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai, case 19200000: /* mclk input, pll disabled */ hppllctl |= TWL6040_MCLK_19200KHZ | - TWL6040_HPLLSQRBP | + TWL6040_HPLLSQRENA | TWL6040_HPLLBP; break; case 26000000: -- 1.6.3.3 _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
