On Wed, Feb 25, 2009 at 05:41:13PM +0100, Daniel Mack wrote: > Is there a thread you can point me to or where have people reported such > things? Grep'ing the archives did unveil anything regarding this. Private e-mail only, sorry. > > The I2S frame length depends on the number of bits per sample. > Well, as far as I got it, these are different things in the register > set. The I2S frame is 64 bits per definition (32 bits for each channel), > and this is what the cs4270 requires to use. Ah, that's not true of I2S devices in general - most only require as many bit clocks as they have data. I've only ever tested with such devices. > The particular problem with the PXA SSP mode is that I've not yet seen a > configuration (neighter in slave nor in master mode) where it sends out > 16 bits of left channel information, followed by 16 bits of zeros, then > 16 bits of right channel and finally another 16bits of zeros (which > exactly what they talk about in the 'i2s via ssp' application note). > Has anyone ever got that? Not to my knowledge. _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
