Re: [PATCH v11 03/10] spi: Add multi-cs memories support in SPI core

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On 1/12/24 11:16, Mark Brown wrote:
On Fri, Jan 12, 2024 at 11:11:07AM -0800, Guenter Roeck wrote:
On Sat, Nov 25, 2023 at 02:51:30PM +0530, Amit Kumar Mahapatra wrote:

AMD-Xilinx GQSPI controller has two advanced mode that allows the
controller to consider two flashes as one single device.

...

With this patch in the mainline kernel, two of my qemu emulations
(quanta-q71l-bmc and almetto-bmc) fail to instantiate the first SPI
controller and thus fail to boot from SPI. The error message is

Not sure what quanta-q711-bmc is - is almetto-bmc really palmetto-bmc
(which has a mainline DT with a SPI flash)?


Yes, sorry, it should have been palmetto-bmc.

quanta-q71l-bmc: See
arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts

(it is q71l, not q711)

Guenter




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