Hi, On Sat, Nov 25, 2023 at 02:51:30PM +0530, Amit Kumar Mahapatra wrote: > AMD-Xilinx GQSPI controller has two advanced mode that allows the > controller to consider two flashes as one single device. > > One of these two mode is the parallel mode in which each byte of data is > stored in both devices, the even bits in the lower flash & the odd bits in > the upper flash. The byte split is automatically handled by the QSPI > controller. > > The other mode is the stacked mode in which both the flashes share the > same SPI bus but each of the device contain half of the data. In this mode, > the controller does not follow CS requests but instead internally wires the > two CS levels with the value of the most significant address bit. > > For supporting both these modes SPI core need to be updated for providing > multiple CS for a single SPI device. > > For adding multi CS support the SPI device need to be aware of all the CS > values. So, the "chip_select" member in the spi_device structure is now an > array that holds all the CS values. > > spi_device structure now has a "cs_index_mask" member. This acts as an > index to the chip_select array. If nth bit of spi->cs_index_mask is set > then the driver would assert spi->chip_select[n]. > > In parallel mode all the chip selects are asserted/de-asserted > simultaneously and each byte of data is stored in both devices, the even > bits in one, the odd bits in the other. The split is automatically handled > by the GQSPI controller. The GQSPI controller supports a maximum of two > flashes connected in parallel mode. A SPI_CONTROLLER_MULTI_CS flag bit is > added in the spi controller flags, through ctlr->flags the spi core > will make sure that the controller is capable of handling multiple chip > selects at once. > > For supporting multiple CS via GPIO the cs_gpiod member of the spi_device > structure is now an array that holds the gpio descriptor for each > chipselect. > > CS GPIO is not tested on our hardware, but it has been tested by @Stefan > https://lore.kernel.org/all/005001da1efc$619ad5a0$24d080e0$@opensource.cirrus.com/ > With this patch in the mainline kernel, two of my qemu emulations (quanta-q71l-bmc and almetto-bmc) fail to instantiate the first SPI controller and thus fail to boot from SPI. The error message is [ 3.006458] spi_master spi0: No. of CS is more than max. no. of supported CS [ 3.006775] spi_master spi0: Failed to create SPI device for /ahb/spi@1e620000/flash@0 The problem is no longer seen after reverting this patch. Bisect log attached for reference. Guenter --- # bad: [70d201a40823acba23899342d62bc2644051ad2e] Merge tag 'f2fs-for-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs # good: [0dd3ee31125508cd67f7e7172247f05b7fd1753a] Linux 6.7 git bisect start 'HEAD' 'v6.7' # bad: [de927f6c0b07d9e698416c5b287c521b07694cac] Merge tag 's390-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux git bisect bad de927f6c0b07d9e698416c5b287c521b07694cac # bad: [35f11a3710cdcbbc5090d14017a6295454e0cc73] Merge tag 'mtd/for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux git bisect bad 35f11a3710cdcbbc5090d14017a6295454e0cc73 # good: [d30e51aa7b1f6fa7dd78d4598d1e4c047fcc3fb9] Merge tag 'slab-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab git bisect good d30e51aa7b1f6fa7dd78d4598d1e4c047fcc3fb9 # good: [fb46e22a9e3863e08aef8815df9f17d0f4b9aede] Merge tag 'mm-stable-2024-01-08-15-31' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm git bisect good fb46e22a9e3863e08aef8815df9f17d0f4b9aede # good: [063a7ce32ddc2c4f2404b0dfd29e60e3dbcdffac] Merge tag 'lsm-pr-20240105' of git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/lsm git bisect good 063a7ce32ddc2c4f2404b0dfd29e60e3dbcdffac # bad: [f6cd66231aa58599526584ff4df1bdde8d86eac8] spi: stm32: add st,stm32mp25-spi compatible supporting STM32MP25 soc git bisect bad f6cd66231aa58599526584ff4df1bdde8d86eac8 # good: [18f78b5e609b19b56237f0dae47068d44b8b0ecd] spi: axi-spi-engine: improvements round 2 git bisect good 18f78b5e609b19b56237f0dae47068d44b8b0ecd # bad: [9d93c8d97b4cdb5edddb4c5530881c90eecb7e44] spi: spi-ti-qspi: switch to use modern name git bisect bad 9d93c8d97b4cdb5edddb4c5530881c90eecb7e44 # bad: [e6b7e64cb11966b26646a362677ca5a08481157e] spi: st-ssc4: switch to use modern name git bisect bad e6b7e64cb11966b26646a362677ca5a08481157e # bad: [c3aeaf2f0ec8af93189488bda3928a1ac7752388] spi: pxa2xx: Use inclusive language git bisect bad c3aeaf2f0ec8af93189488bda3928a1ac7752388 # good: [f05e2f61fe88092e0d341ea27644a84e3386358d] ALSA: hda/cs35l56: Use set/get APIs to access spi->chip_select git bisect good f05e2f61fe88092e0d341ea27644a84e3386358d # bad: [88a50c1663ffa9f6b31705c6bf7a887a2c8d9434] spi: Add support for stacked/parallel memories git bisect bad 88a50c1663ffa9f6b31705c6bf7a887a2c8d9434 # bad: [4d8ff6b0991d5e86b17b235fc46ec62e9195cb9b] spi: Add multi-cs memories support in SPI core git bisect bad 4d8ff6b0991d5e86b17b235fc46ec62e9195cb9b # first bad commit: [4d8ff6b0991d5e86b17b235fc46ec62e9195cb9b] spi: Add multi-cs memories support in SPI core
