On 12/8/23 10:27, Charles Keepax wrote: > On Thu, Dec 07, 2023 at 04:29:29PM -0600, Pierre-Louis Bossart wrote: >> The Bulk Register Access protocol was left as a TODO topic since >> 2018. It's time to document this protocol and the design of its Linux >> support. >> >> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@xxxxxxxxxxxxxxx> >> --- >> +Concurrency between BRA and regular read/write >> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> + >> +The existing 'nread/nwrite' API already relies on a notion of start >> +address and number of bytes, so it would be possible to extend this >> +API with a 'hint' requesting BPT/BRA be used. >> + >> +However BRA transfers could be quite long, and the use of a single >> +mutex for regular read/write and BRA is a show-stopper. Independent >> +operation of the control/command and BRA transfers is a fundamental >> +requirement, e.g. to change the volume level with the existing regmap >> +interface while downloading firmware. > > Is this definitely a show stopper? Not saying that it wouldn't be > desirable to do both from a speed perspective, but current > systems that download firmware (I2C/SPI) typically will block the > bus for some amount of time. There are also some desirable properties > to a single lock such as not needing to worry about accessing the > same register in the bulk transfer and a normal command transfer. There are other cases where we do want to interact with the device even if we are in the middle of downloading stuff. We currently have a msg_lock that's used to prevent multiple read/writes from being sent on the bus, I really don't think it would be wise to use this same "lightweight" lock for much longer transfers. This could impact response to alerts, changes in state reported by the hardware, etc. >> +Audio DMA support >> +----------------- >> + >> +Some DMAs, such as HDaudio, require an audio format field to be >> +set. This format is in turn used to define acceptable bursts. BPT/BRA >> +support is not fully compatible with these definitions in that the >> +format may vary between read and write commands. >> + >> +In addition, on Intel HDaudio Intel platforms the DMAs need to be >> +programmed with a PCM format matching the bandwidth of the BPT/BRA >> +transfer. The format is based on 48kHz 32-bit samples, and the number >> +of channels varies to adjust the bandwidth. The notion of channel is >> +completely notional since the data is not typical audio >> +PCM. Programming channels helps reserve enough bandwidth and adjust >> +FIFO sizes to avoid xruns. Note that the quality of service comes as a >> +cost. Since all channels need to be present as a sample block, data >> +sizes not aligned to 128-bytes are not supported. > > Apologies but could you elaborate a litte on this? I am not sure > I follow the reasoning, how does the 48k 32bit DMA implementation > result in 128-byte limitation? I would have thought 1 channel would > be 4-bytes and you are varying the channels so I would have expected > 4-byte aligned maybe 8-byte if the DMA expects stereo pairs. With the 50x4 default frame size that we're using, a BTP/BRA write requires 13.824 Mbits/s for TX and 3.072Mbits/s for RX. We have to treat these "non-audio' streams as respectively 10 and 2 channels of 48kHz 32bit data to reserve the equivalent PCM bandwidth, and that creates an alignment requirement since the DMA expects all 'channels' to be present in the same block. We could try and play with parameters, e.g. I am not sure what happens if we used 192kHz, maybe that reduces the alignment back to 32 bytes. But the point is arbitrary sizes *cannot* be handled. The HDaudio spec also mentions that for efficiency reason it's strongly recommended to use 128-byte multiples. > And what exactly do we mean by aligned, are we saying the length > all transfers needs to be a multiple of 128-bytes? Yes. > I think we might have some annoying restrictions on the block > size on our hardware as well I will go dig into that and report > back. That would be very useful indeed, we have to make sure this alignment is reasonably supported across hosts and devices. If we can't agree we'll have to make the alignment host-dependent, but that will make the logic in codec drivers more complicated.
