On Tue, Mar 21, 2023 at 07:09:43PM +0200, Marian Postevca wrote: > Mark Brown <broonie@xxxxxxxxxx> writes: > > On Mon, Mar 20, 2023 at 10:35:16PM +0200, Marian Postevca wrote: > > This introduces a DT property but there's no documentation for it, but I > > don't see why we'd want this in the bindings - the driver should be able > > to tell from the input clock rate and required output/internal clocks if > > it needs to divide MCLK. > The problem here is that I have no knowledge what is the maximum MCLK > that the codec accepts. According to the datasheet the maximum supported > frequency of MCLK is 51.2 Mhz. But this doesn't seem to be the case in > practice since a MCLK of 48Mhz causes noises in the sound output. > The idea to divide the MCLK by 2 was proposed by a Everest Semiconductor > engineer. > So I don't know how to make this generic enough to be activated from the > codec driver. The usual constraint would be that MCLK can be at most some multiple of LRCLK or something similar (are all the other dividers in the chip set sensibly for the full scale MCLK?). In any case you're clearly aware of a specific case where it needs to be divided down which can be identified even if you're concerned about dividing down for other cases.
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