On Wed, Nov 09, 2022 at 08:13:54PM +0800, Chancel Liu wrote: > DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate > correct frequency of LRCLK and BCLK. Sometimes the read-only value > can't be updated timely after enabling SYSCLK. This results in wrong > calculation values. Delay is introduced here to wait for newest value > from register. The time of the delay should be at least 500~1000us > according to test. > > Signed-off-by: Chancel Liu <chancel.liu@xxxxxxx> > --- Acked-by: Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx> Thanks, Charles
