On Fri, Mar 5, 2021 at 1:15 AM Shengjiu Wang <shengjiu.wang@xxxxxxx> wrote: > > With S20_3LE format case, the sysclk = rate * 384, > the bclk = rate * 20 * 2, there is no proper bclk divider > for 384 / 40, because current condition needs exact match. > So driver fails to configure the clocking: > > wm8962 3-001a: Unsupported BCLK ratio 9 > > Fix this by relaxing bitclk divider searching, so that when > no exact value can be derived from sysclk pick the closest > value greater than expected bitclk. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@xxxxxxx> Reviewed-by: Daniel Baluta <daniel.baluta@xxxxxxx>
