On Wed, Mar 03, 2021 at 07:21:28PM +0800, Shengjiu Wang wrote: > With S20_3LE format case, the sysclk = rate * 384, > the bclk = rate * 20 * 2, there is no proper bclk divider > for 384 / 40, because current condition needs exact match. > So driver fails to configure the clocking: > > wm8962 3-001a: Unsupported BCLK ratio 9 > > Fix this by relaxing bitclk divider searching, so that when > no exact value can be derived from sysclk pick the closest > value greater than expected bitclk. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@xxxxxxx> > --- > sound/soc/codecs/wm8962.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c > index ce4666a74793..f5cd22450190 100644 > --- a/sound/soc/codecs/wm8962.c > +++ b/sound/soc/codecs/wm8962.c > @@ -2403,6 +2403,7 @@ static const int sysclk_rates[] = { > static void wm8962_configure_bclk(struct snd_soc_component *component) > { > struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); > + int best, min_diff, diff; > int dspclk, i; > int clocking2 = 0; > int clocking4 = 0; > @@ -2473,23 +2474,23 @@ static void wm8962_configure_bclk(struct snd_soc_component *component) > > dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); > Very minor nit but it would probably be nice to have some equivalent debug statement that prints out the actual BCLK we end up with. There are a couple of statements printing the requested speed, but nothing that will output what the driver actually applies after this change. Otherwise I think the change looks good. Thanks, Charles