On Wed, Sep 30, 2020 at 09:11:24PM -0500, Samuel Holland wrote: > The sun8i codec is effectively an on-die variant of the X-Powers AC100 > codec. The AC100 can derive its clocks from either of two I2S master > clocks or an internal PLL. For the on-die variant, Allwinner replaced > the codec's own PLL with a connection to SoC's existing PLL_AUDIO, and > they connected both I2S MCLK inputs to the same source -- which happens > to be an integer divider from the same PLL_AUDIO. > > So there's actually no clocking flexibility. To run SYSCLK at the > required rate, it must be run straight from the PLL. The only choice is > whether it goes through AIF1CLK or AIF2CLK. Since both run at the same > rate, the only effect of that choice is which field in SYS_SR_CTRL > (AIF1_FS or AIF2_FS) controls the system sample rate. > > Since AIFnCLK is required to bring up the corresponding DAI, and AIF1 > (connected to the CPU) is used most often, let's use AIF1CLK as the > SYSCLK parent. That means we no longer need to set AIF2_FS. > > Since this clock tree never changes, we can program it from the > component probe function, instead of using DAPM widgets. The DAPM > widgets unnecessarily change clock parents when the codec goes in/out > of idle and the supply widgets are powered up/down. > > Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> Acked-by: Maxime Ripard <mripard@xxxxxxxxxx> Maxime
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