Re: Is there a convention for mapping codec vendor's register::bit names to alsa control names?

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Title: RE: Is there a convention for mapping codec vendor's register::bit names to alsa control names?

PLz forgive if you see this twice, outlook web access is tormenting me further


-----Original Message-----
From: Takashi Iwai [mailto:tiwai@xxxxxxx]
Sent: Fri 2/23/2007 7:19 AM
To: John Utz
Cc: alsa-devel@xxxxxxxxxxxxxxxxxxxxx
Subject: Re: Is there a convention for mapping codec vendor's register::bit names to alsa control names?

At Thu, 22 Feb 2007 10:04:20 -0800,
John Utz wrote:
>
> * If no, we can hardcode these bits in the initialization sequence.
>
> these bits form a matrix that configure some combinations of mic ins, line ins and
> surround outputs.
>
> In the case of somebody that has a full collection of plugins/plugouts, their surround
> output might not work as expected.
>
> And, that person might want to sometimes change the line in and the speaker out to be
> more mic inputs.
>
> So surfacing flexibility to the end user is important.
>
> The problem with surfacing this is that matrix is pretty hard to follow:
>
> 1. the doc has some bugs; ie SM51 and SMIC are not the names of the bits
>
> 2. the collection of choices is so strange that it looks like the result of running a
> gate minimization program instead of choosing the matrix based on user need :-)
>
>     Controller Bit     MICIN                 I/O
> SM51 SM51SW SMIC 20XL 20XR     MIC1 MIC2  MIC3    LL   LR
>  0        0        0 MIC1 MIC1 MIC1   -    -      LL   LR
>  0        0        1 MIC1 MIC3 MIC1   -   MIC3    LL   LR
>  0        1        0 MIC2 MIC2   -  MIC2   -      LL   LR
>  0        1        1 MIC1 MIC2 MIC1 MIC2   -      LL   LR
>  1        0        0 MIC3 MIC3 CEN   LFE  MIC3   SURL SURR
>  1        0        1 MIC3 MIC3 CENT  LFE  MIC3    LL   LR
>  1        1        0 MIC1 MIC1 Mic1       LFE    SURL SURR
>  1        1        1 MIC1 MIC2 MIC1 MIC2- LFE    SURL SURR
>
> If somebody can make sense of this by assigning a simple meaning to each input bit in
> this karnaugh map then i'd welcome that insight!
>
> However, having looked at this for several hours, I think this is already minimized.

* Well, too minimized to understand quite what they mean :)
* Could you explain a bit more detail?


yes, certainly! this matrix is called 'Mixer Table'


The bit's are as follows, complete with documentation mistakes :


SM51 is a mistake, it's listed in the docs as SM51EN. it has a 1 line decription:

  'Smart 5.1 feature (See Mixer Table)'


SM51SW is corrent, it has a 1 line description:

  'Smart 5.1 feature (See Mixer Table)'


SMIC is a mistake, it's listed in the docs as MS, it has a 1 line description:

  'Microphone Select (See Table Below)'


20XL i have NO IDEA what this is.

20XR i have NO IDEA what this is.


MIC{1,2,3} i ASSUME are routing for different mic inputs


L{L,R} i am pretty sure is Line In Left and Right

S{L,R} is Surround Left and Right

CEN and LFE are Center and Low Frequency Enhancement


These are the different choices in the matrix, i dont like the idea of arbitrarily picking a setup that turns on surround and ignores the other choices.

My current code surfaces all 3 bits:

  AC97_SINGLE("Smart 5.1 Control A", 0x20,  8, 1, 0),
  AC97_SINGLE("Smart 5.1 Control B", 0x7a, 15, 1, 0),
  AC97_SINGLE("Smart 5.1 Control C", 0x7a, 14, 1, 0)

I havent come up with any better idea.

tnx for any thoughts you may have.


johnu

* Takashi


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