Re: [PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

[Peng Fan <peng.fan@xxxxxxxxxxx>]

On Thu, Dec 26, 2024 at 05:22:24PM +0100, Marek Vasut wrote:
>The driver currently supports generating BCLK. There are systems which
>require generation of MCLK instead. Register new MCLK clock and handle
>clock-cells = <1> to differentiate between BCLK and MCLK. In case of a
>legacy system with clock-cells = <0>, the driver behaves as before, i.e.
>always returns BCLK.
>
>Signed-off-by: Marek Vasut <marex@xxxxxxx>
>---
>Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
>Cc: Fabio Estevam <festevam@xxxxxxxxx>
>Cc: Jaroslav Kysela <perex@xxxxxxxx>
>Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
>Cc: Liam Girdwood <lgirdwood@xxxxxxxxx>
>Cc: Mark Brown <broonie@xxxxxxxxxx>
>Cc: Michael Turquette <mturquette@xxxxxxxxxxxx>
>Cc: Michael Walle <michael@xxxxxxxx>
>Cc: Nicolin Chen <nicoleotsuka@xxxxxxxxx>
>Cc: Rob Herring <robh@xxxxxxxxxx>
>Cc: Shengjiu Wang <shengjiu.wang@xxxxxxxxx>
>Cc: Stephen Boyd <sboyd@xxxxxxxxxx>
>Cc: Takashi Iwai <tiwai@xxxxxxxx>
>Cc: Xiubo Li <Xiubo.Lee@xxxxxxxxx>
>Cc: devicetree@xxxxxxxxxxxxxxx
>Cc: linux-clk@xxxxxxxxxxxxxxx
>Cc: linux-sound@xxxxxxxxxxxxxxx
>---
>V2: No change
>---
> drivers/clk/clk-fsl-sai.c | 81 ++++++++++++++++++++++++++++++++-------
> 1 file changed, 67 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
>index 628e53a3a26fa..0f8e2f2662d87 100644
>--- a/drivers/clk/clk-fsl-sai.c
>+++ b/drivers/clk/clk-fsl-sai.c
>@@ -7,6 +7,7 @@
> 
> #include <linux/module.h>
> #include <linux/platform_device.h>
>+#include <linux/clk.h>
> #include <linux/clk-provider.h>
> #include <linux/err.h>
> #include <linux/of.h>
>@@ -15,27 +16,44 @@
> 
> #define I2S_CSR		0x00
> #define I2S_CR2		0x08
>+#define I2S_MCR		0x100
> #define CSR_BCE_BIT	28
>+#define CSR_TE_BIT	31
> #define CR2_BCD		BIT(24)
> #define CR2_DIV_SHIFT	0
> #define CR2_DIV_WIDTH	8
>+#define MCR_MOE		BIT(30)
> 
> struct fsl_sai_clk {
>-	struct clk_divider div;
>-	struct clk_gate gate;
>+	struct clk_divider bclk_div;
>+	struct clk_divider mclk_div;
>+	struct clk_gate bclk_gate;
>+	struct clk_gate mclk_gate;
>+	struct clk_hw *bclk_hw;
>+	struct clk_hw *mclk_hw;
> 	spinlock_t lock;
> };
> 
> struct fsl_sai_data {
> 	unsigned int	offset;	/* Register offset */
>+	bool		have_mclk; /* Have MCLK control */
> };
> 
>+static struct clk_hw *
>+fsl_sai_of_clk_get(struct of_phandle_args *clkspec, void *data)
>+{
>+	struct fsl_sai_clk *sai_clk = data;
>+
>+	return clkspec->args[0] ? sai_clk->mclk_hw : sai_clk->bclk_hw;
>+}
>+
> static int fsl_sai_clk_probe(struct platform_device *pdev)
> {
> 	struct device *dev = &pdev->dev;
> 	const struct fsl_sai_data *data = device_get_match_data(dev);
>-	struct fsl_sai_clk *sai_clk;
> 	struct clk_parent_data pdata = { .index = 0 };
>+	struct fsl_sai_clk *sai_clk;
>+	struct clk *clk_bus;
> 	void __iomem *base;
> 	struct clk_hw *hw;
> 
>@@ -47,39 +65,74 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
> 	if (IS_ERR(base))
> 		return PTR_ERR(base);
> 
>+	clk_bus = devm_clk_get_enabled(dev, "bus");
>+	if (IS_ERR(clk_bus))
>+		return PTR_ERR(clk_bus);
>+

This only applies to i.MX? 

> 	spin_lock_init(&sai_clk->lock);
> 

Regards,
Peng