On Wed, Jan 11, 2017 at 01:31:02AM +0000, Qiao, Liyong wrote: > > > Also, why only l3 cache. Why not expose full info about > > the CPU cache hierarchy. It feels wrong to expose only > > L3 cache and ignore other levels of cache. > > Okay, I’ll think how to expose there into capabilities. This is related to enable cache tune support in [1] > The status in kernel is that only L3 cache can be tuned(by cat_l3 support in kernel) for now. Right, but that's a characteristic of a specific hardware version. We need to consider that there may be future changes, or that different architectures may come up with different support status. So I'd rather see us fully describe the cache availability, rather than assume that L3 is the only thing we ever need to describe. Regards, Daniel -- |: http://berrange.com -o- http://www.flickr.com/photos/dberrange/ :| |: http://libvirt.org -o- http://virt-manager.org :| |: http://entangle-photo.org -o- http://search.cpan.org/~danberr/ :| -- libvir-list mailing list libvir-list@xxxxxxxxxx https://www.redhat.com/mailman/listinfo/libvir-list
