On Thu, Dec 24, 2009 at 8:30 AM, Rangeen Basu <sherry151@xxxxxxxxx> wrote: > Hi > > @subject > > Anything similar to alliance( VHDL) for Verilog? Hello, Actually not a real one. You can use "vasy" to translate verilog structural design to a vhdl one. Else you can use iverilog to translate the verilog structural design to a vhdl one. Once you have the vhdl equivalent, you can resume the normal flow. However the verilog to vhdl translations are not perfect, but I would say try both conversions and benchmark the outcomes. I believe iverilog's translator is a better one. I'm curious about the outcomes. Let us know your progress. Chitlesh _______________________________________________ Fedora-electronic-lab-list mailing list Fedora-electronic-lab-list@xxxxxxxxxx https://www.redhat.com/mailman/listinfo/fedora-electronic-lab-list
