Hello Vince,
Thanks for the work you've done to get 8 cores working on the
Odroid-XU4. Here is the output you asked of Andreas from my XU4
running the latest fedora kernel:
[root@myodroid-wireless ~]# uname -a
Linux myodroid-wireless 4.17.18-200.fc28.armv7hl #1 SMP Wed Aug
22 20:36:45 UTC 2018 armv7l armv7l armv7l GNU/Linux
[root@myodroid-wireless ~]#
[root@myodroid-wireless ~]# lsusb -t
/: Bus 06.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p,
5000M
/: Bus 05.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p,
480M
|__ Port 1: Dev 2, If 0, Class=Vendor Specific Class,
Driver=r8152, 480M
/: Bus 04.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p,
5000M
|__ Port 1: Dev 2, If 0, Class=Hub, Driver=hub/2p, 5000M
|__ Port 1: Dev 3, If 0, Class=Hub, Driver=hub/4p, 5000M
|__ Port 1: Dev 4, If 0, Class=Hub, Driver=hub/4p,
5000M
/: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p,
480M
|__ Port 1: Dev 2, If 0, Class=Hub, Driver=hub/2p, 480M
|__ Port 1: Dev 3, If 0, Class=Hub, Driver=hub/4p, 480M
|__ Port 1: Dev 5, If 0, Class=Hub, Driver=hub/4p,
480M
|__ Port 2: Dev 6, If 0, Class=Hub,
Driver=hub/4p, 12M
|__ Port 4: Dev 9, If 2, Class=Human
Interface Device, Driver=usbhid, 12M
|__ Port 4: Dev 9, If 0, Class=Human
Interface Device, Driver=usbhid, 12M
|__ Port 4: Dev 9, If 1, Class=Human
Interface Device, Driver=usbhid, 12M
|__ Port 2: Dev 8, If 1, Class=Wireless,
Driver=btusb, 12M
|__ Port 2: Dev 8, If 0, Class=Wireless,
Driver=btusb, 12M
|__ Port 1: Dev 7, If 2, Class=Human
Interface Device, Driver=usbhid, 12M
|__ Port 1: Dev 7, If 0, Class=Human
Interface Device, Driver=usbhid, 12M
|__ Port 1: Dev 7, If 1, Class=Human
Interface Device, Driver=usbhid, 12M
|__ Port 2: Dev 4, If 0, Class=Vendor Specific Class,
Driver=rtl8192cu, 480M
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=exynos-ohci/3p,
12M
/: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=exynos-ehci/3p,
480M
Also, here is some other output of interest:
[root@myodroid-wireless ~]# cpupower frequency-info
analyzing CPU 0:
driver: cpufreq-dt
CPUs which run at the same hardware frequency: 0 1 2 3
CPUs which need to have their frequency coordinated by
software: 0 1 2 3
maximum transition latency: 154 us
hardware limits: 200 MHz - 1.30 GHz
available frequency steps: 200 MHz, 300 MHz, 400 MHz, 500
MHz, 600 MHz, 700 MHz, 800 MHz, 900 MHz, 1000 MHz, 1.10 GHz,
1.20 GHz, 1.30 GHz
available cpufreq governors: conservative userspace powersave
ondemand performance schedutil
current policy: frequency should be within 200 MHz and 1.30
GHz.
The governor "ondemand" may decide which speed
to use
within this range.
current CPU frequency: 700 MHz (asserted by call to hardware)
[root@myodroid-wireless ~]# cpupower frequency-info --governors
analyzing CPU 0:
available cpufreq governors: conservative userspace powersave
ondemand performance schedutil
[root@myodroid-wireless ~]# cpupower frequency-set --governor
performance
Setting cpu: 0
Setting cpu: 1
Setting cpu: 2
Setting cpu: 3
Setting cpu: 4
Setting cpu: 5
Setting cpu: 6
Setting cpu: 7
[root@myodroid-wireless ~]# cpupower frequency-info
analyzing CPU 0:
driver: cpufreq-dt
CPUs which run at the same hardware frequency: 0 1 2 3
CPUs which need to have their frequency coordinated by
software: 0 1 2 3
maximum transition latency: 154 us
hardware limits: 200 MHz - 1.30 GHz
available frequency steps: 200 MHz, 300 MHz, 400 MHz, 500
MHz, 600 MHz, 700 MHz, 800 MHz, 900 MHz, 1000 MHz, 1.10 GHz,
1.20 GHz, 1.30 GHz
available cpufreq governors: conservative userspace powersave
ondemand performance schedutil
current policy: frequency should be within 200 MHz and 1.30
GHz.
The governor "performance" may decide which
speed to use
within this range.
current CPU frequency: 1.30 GHz (asserted by call to hardware)
[root@myodroid-wireless ~]# lscpu
Architecture: armv7l
Byte Order: Little Endian
CPU(s): 8
On-line CPU(s) list: 0-7
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 2
Vendor ID: ARM
Model: 3
Model name: Cortex-A7
Stepping: r0p3
CPU max MHz: 1800.0000
CPU min MHz: 200.0000
BogoMIPS: 78.00
Flags: half thumb fastmult vfp edsp thumbee neon
vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
[root@myodroid-wireless ~]# dmesg
[ 0.000000] Booting Linux on physical CPU 0x100
[ 0.000000] Linux version 4.17.18-200.fc28.armv7hl
(mockbuild@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) (gcc version
8.1.1 20180712 (Red Hat 8.1.1-5) (GCC)) #1 SMP Wed Aug 22
20:36:45 UTC 2018
[ 0.000000] CPU: ARMv7 Processor [410fc073] revision 3
(ARMv7), cr=10c5387d
[ 0.000000] CPU: div instructions available: patching
division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT
aliasing instruction cache
[ 0.000000] OF: fdt: Machine model: Hardkernel Odroid XU4
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] cma: Reserved 192 MiB at 0xb2800000
[ 0.000000] Samsung CPU ID: 0xe5422001
[ 0.000000] On node 0 totalpages: 518656
[ 0.000000] Normal zone: 1728 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 196608 pages, LIFO batch:31
[ 0.000000] HighMem zone: 322048 pages, LIFO batch:31
[ 0.000000] Running under secure firmware.
[ 0.000000] random: fast init done
[ 0.000000] percpu: Embedded 16 pages/cpu @(ptrval) s34572
r8192 d22772 u65536
[ 0.000000] pcpu-alloc: s34572 r8192 d22772 u65536
alloc=16*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5
[0] 6 [0] 7
[ 0.000000] Built 1 zonelists, mobility grouping on. Total
pages: 516928
[ 0.000000] Kernel command line: ro
rd.driver.pre=ledtrig-heartbeat,xhci-plat-hcd
root=UUID=d4a4b86d-5e86-4bcb-b79c-2bde6831b7c5 cma=192MB
cpuidle.off=1 LANG=en_US.UTF-8 no_bL_switcher
[ 0.000000] Dentry cache hash table entries: 131072 (order:
7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6,
262144 bytes)
[ 0.000000] Memory: 1822580K/2074624K available (8168K kernel
code, 1328K rwdata, 3920K rodata, 2048K init, 505K bss, 55436K
reserved, 196608K cma-reserved, 1091584K highmem)
[ 0.000000] Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
.text : 0x(ptrval) - 0x(ptrval) (9161 kB)
.init : 0x(ptrval) - 0x(ptrval) (2048 kB)
.data : 0x(ptrval) - 0x(ptrval) (1329 kB)
.bss : 0x(ptrval) - 0x(ptrval) ( 506 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0,
CPUs=8, Nodes=1
[ 0.000000] ftrace: allocating 37441 entries in 74 pages
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=32 to
nr_cpu_ids=8.
[ 0.000000] Tasks RCU enabled.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16,
nr_cpu_ids=8
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] GIC physical location is 0x10481000
[ 0.000000] Switching to timer-based delay loop, resolution
41ns
[ 0.000000] clocksource: mct-frc: mask: 0xffffffff
max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
[ 0.000007] sched_clock: 32 bits at 24MHz, resolution 41ns,
wraps every 89478484971ns
[ 0.000033] genirq: irq_chip COMBINER did not update eff.
affinity mask of irq 49
[ 0.006905] Console: colour dummy device 80x30
[ 0.007535] console [tty0] enabled
[ 0.007603] Calibrating delay loop (skipped), value
calculated using timer frequency.. 48.00 BogoMIPS (lpj=24000)
[ 0.007640] pid_max: default: 32768 minimum: 301
[ 0.007903] Security Framework initialized
[ 0.007927] Yama: becoming mindful.
[ 0.007994] SELinux: Initializing.
[ 0.008199] SELinux: Starting in permissive mode
[ 0.008297] Mount-cache hash table entries: 2048 (order: 1,
8192 bytes)
[ 0.008335] Mountpoint-cache hash table entries: 2048 (order:
1, 8192 bytes)
[ 0.009575] CPU: Testing write buffer coherency: ok
[ 0.010559] CPU0: thread -1, cpu 0, socket 1, mpidr 80000100
[ 0.011506] Setting up static identity map for 0x40300000 -
0x403000a0
[ 0.012297] ARM CCI driver probed
[ 0.012546] Exynos MCPM support installed
[ 0.015526] Hierarchical SRCU implementation.
[ 0.022460] EFI services will not be available.
[ 0.023397] smp: Bringing up secondary CPUs ...
[ 0.024680] CPU1: thread -1, cpu 1, socket 1, mpidr 80000101
[ 0.026094] CPU2: thread -1, cpu 2, socket 1, mpidr 80000102
[ 0.027452] CPU3: thread -1, cpu 3, socket 1, mpidr 80000103
[ 0.028759] CPU4: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.030181] CPU5: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.031561] CPU6: thread -1, cpu 2, socket 0, mpidr 80000002
[ 0.032919] CPU7: thread -1, cpu 3, socket 0, mpidr 80000003
[ 0.033125] smp: Brought up 1 node, 8 CPUs
[ 0.033262] SMP: Total of 8 processors activated (384.00
BogoMIPS).
[ 0.033284] CPU: WARNING: CPU(s) started in
wrong/inconsistent modes (primary CPU mode 0x1a)
[ 0.033309] CPU: This may indicate a broken bootloader or
firmware.
Note the following:
- Although 8 cores are recognized, the "lscpu" command (and the
"dmesg" snippet) recognizes only the A7 processor.
- The default cpu governor is "ondemand" providing a cpu
frequency of 700 MHz for all cores per the output of the first
"cpupower frequency-info" above.
- The cpu governor and frequency can be changed to "performance"
and 1300 MHz, respectively by using the command "cpupower
frequency-set --governor performance", but this is not
persistent between reboots. To make it persistent between
reboots follow this procedure:
https://ask.fedoraproject.org/en/question/39964/how-to-permanently-set-cpu-power-management-to-the-powersave-governor
- Note the last two lines in the "dmesg" command. There may be
additional code required in the bootloader or firmware to
recognize the A15 processor correctly. Does anyone have any
ideas here?
Stewart
On 08/27/2018 01:41 AM, Vince Geze
wrote:
-----Original Message-----
From: Andreas Reschke [mailto:arm_ml@xxxxxxxxxxx]
Sent: Saturday, August 25, 2018 11:50 AM
To: Vince Geze <vincegeze@xxxxxxxxx>
Cc: arm@xxxxxxxxxxxxxxxxxxxxxxx
Subject: Re: [fedora-arm] Re: F28 on odroid XU4
Am 24.08.2018 um 15:15 schrieb Vince Geze:
-----Original Message-----
From: arm_ml@xxxxxxxxxxx [mailto:arm_ml@xxxxxxxxxxx]
Sent: Friday, August 24, 2018 2:45 PM
To: Vince Geze <vincegeze@xxxxxxxxx>
Cc: arm@xxxxxxxxxxxxxxxxxxxxxxx
Subject: Re: [fedora-arm] Re: F28 on odroid XU4
Am 2018-08-24 14:37, schrieb Vince Geze:
-----Original Message-----
From: arm_ml@xxxxxxxxxxx [mailto:arm_ml@xxxxxxxxxxx]
Sent: Friday, August 24, 2018 2:27 PM
To: Vince Geze <vincegeze@xxxxxxxxx>
Cc: arm@xxxxxxxxxxxxxxxxxxxxxxx
Subject: Re: [fedora-arm] Re: F28 on odroid XU4
Am 2018-08-24 14:17, schrieb Vince Geze:
-----Original Message-----
From: arm_ml@xxxxxxxxxxx [mailto:arm_ml@xxxxxxxxxxx]
Sent: Friday, August 24, 2018 1:39 PM
To: Vince Geze <vincegeze@xxxxxxxxx>
Cc: arm@xxxxxxxxxxxxxxxxxxxxxxx
Subject: Re: [fedora-arm] Re: F28 on odroid XU4
Am 2018-08-24 12:09, schrieb Vince Geze:
--snip--
Well, after countless reboots it seems to be even more simple.
- USB3: preloading xhci-plat-hcd, which already is in the
initramfs, is sufficient to get proper USB3 operation and the
r8152 at full speed as well
- CPU HMP: this one I already knew was linked to the
CONFIG_BL_SWITCHER. On [1] it is mentioned there are both sysfs
and kernel boot options to control this behavior. The sysfs path
exists and with lscpu you can see all 8 cores being put online.
The kernel boot command however turned out to be incorrect, but
after some digging I found you only need "no_bL_switcher" as
boot
option.
Since the board will be used headless, I also enabled the
blinking led by preloading ledtrig-heartbeat, but this needs to
be included in a /etc/dracut.conf.d/ conf file with
'add_drivers+="
ledtrig-heartbeat "'. The blinking frequency also gives an
indication
of
the load.
The final boot line now looks like this:
append ro rd.driver.pre=ledtrig-heartbeat,xhci-plat-hcd
root=UUID=your_UUID cpuidle.off=1 no_bL_switcher console=tty1
console=ttySAC2,115200n8
Result:
- systematically correct detection of USB3
- performance improvement by enabling all cpus
- indication whether the system is alive or not
- no need for recompiling kernels, only boot time options and an
optional dracut inclusion
Best regards,
Vince
[1]
https://wiki.linaro.org/projects/big.LITTLE.MP/Big.Little.Switch
er/
Doc
s/porting-guide
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Hello Vince,
I must say thank you !
With your work I can enable all 8 CPUs on my Odroid HC1.
lscpu before:
[root@odroidh1 ~]# lscpu
Architektur: armv7l
Byte-Reihenfolge: Little Endian
CPU(s): 8
Liste der Online-CPU(s): 0-3
Liste der Offline-CPU(s): 4-7
Thread(s) pro Kern: 1
Kern(e) pro Socket: 4
Sockel: 1
lscpu after:
Architektur: armv7l
Byte-Reihenfolge: Little Endian
CPU(s): 8
Liste der Online-CPU(s): 0-7
Thread(s) pro Kern: 1
Kern(e) pro Socket: 4
Sockel: 2
Greetings
Andreas
Hi Andreas,
Glad to hear it's working on your side as well. Could you also
check the number at the end of the r8152 line in lsusb -t with the
default boot line without preloads? Is it 480M or 5000M?
Best regards,
Vince
System without your modifikation:
[root@odroidh1 ~]# lsusb -t
/: Bus 06.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 5000M
/: Bus 05.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 480M
|__ Port 1: Dev 2, If 0, Class=Vendor Specific Class,
Driver=r8152,
480M
/: Bus 04.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 5000M
|__ Port 1: Dev 2, If 0, Class=Mass Storage, Driver=uas,
5000M
/: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 480M
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=exynos-ehci/3p,
480M
/: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=exynos-ohci/3p,
12M
[root@odroidh1 ~]#
System with your modifikation:
[root@odroidh2 ~]# lsusb -t
/: Bus 06.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 5000M
/: Bus 05.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 480M
|__ Port 1: Dev 2, If 0, Class=Vendor Specific Class,
Driver=r8152,
480M
/: Bus 04.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 5000M
|__ Port 1: Dev 2, If 0, Class=Mass Storage, Driver=uas,
5000M
/: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 480M
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=exynos-ehci/3p,
480M
/: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=exynos-ohci/3p,
12M
[root@odroidh2 ~]#
Systems are identical: Odroid HC1 with update Fedora 28
Andreas
Hi Andreas,
Looks like the storage is working at USB3 speed, but the Ethernet at
USB2.
Have you included the xhci preload at the modified boot line?
Best regards,
Vince
Yes of course:
[root@odroidh2 ~]# cat /boot/extlinux/extlinux.conf # extlinux.conf
generated by appliance-creator ui menu.c32 menu autoboot Welcome to
Fedora-Minimal-armhfp-28-1.1. Automatic boot in # second{,s}. Press a
key for options.
menu title Fedora-Minimal-armhfp-28-1.1 Boot Options.
menu hidden
timeout 20
totaltimeout 600
default=Fedora (4.17.14-202.fc28.armv7hl) 28 (Twenty Eight) label
Fedora
(4.17.14-202.fc28.armv7hl) 28 (Twenty Eight)
kernel /vmlinuz-4.17.14-202.fc28.armv7hl
append ro rd.driver.pre=ledtrig-heartbeat,xhci-plat-hcd
root=UUID=cf0c90a1-25e4-429b-a77e-b9b4f3802258 cpuidle.off=1
LANG=de_DE.UTF-8 no_bL_switcher console=tty1 console=ttySAC2,1152
00n8
fdtdir /dtb-4.17.14-202.fc28.armv7hl/
initrd /initramfs-4.17.14-202.fc28.armv7hl.img
[root@odroidh2 ~]#
I've edit this line with the older kernel before I updated the system
this kernel.
Andreas
Hi Andreas,
Have you removed power completely between reboots, meaning
physically
unplug power at board side for 5-10 seconds such that all leds are
dimmed? I have the impression not every component is fully or
correctly reset if you just do an init 6. It would be quite
interesting to know if that could be the issue with the r8152 driver,
since, except for the heartbeat, adding those options to the original
4.16 kernel of the F28 image without any dracut initramfs regeneration was
sufficient on my device.
Best regards,
Vince
Hello Vince,
after newest kernel update and poweroff for 1 minute:
[root@odroidh2 ~]# lsusb -t
/: Bus 06.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 5000M
|__ Port 1: Dev 2, If 0, Class=Vendor Specific Class, Driver=r8152, 5000M
/: Bus 05.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 480M
/: Bus 04.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 5000M
|__ Port 1: Dev 2, If 0, Class=Mass Storage, Driver=uas, 5000M
/: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 480M
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=exynos-ehci/3p, 480M
/: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=exynos-ohci/3p, 12M
[root@odroidh2 ~]# uname -a
Linux odroidh2.reschke.lan 4.17.17-200.fc28.armv7hl #1 SMP Mon Aug 20
17:31:32 UTC 2018 armv7l armv7l armv7l GNU/Linux
[root@odroidh2 ~]#
Greetings
Andreas
Hi Andreas,
Thanks for the feedback, looks like both storage and Ethernet are connected as USB3 now.
Out of curiosity, are you running from SD or eMMC? I'm still using SD for testing, but once I got everything covered I'd like to switch to eMMC.
Best regards,
Vince
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