libvirt supports guest CPU cache by commit df13c0b, So add this feature
to virt-install to configure cpu L3 cache mode.
Currently, The valid values are 'passthrough', 'emulate' or 'disable'.
say:
--cpu host-passthrough,cache.mode=passthrough
or
--cpu $CPU,cache.mode=emulate,cache.level=3
or
--cpu $CPU,cache.mode=disable
Signed-off-by: Lin Ma <lma@xxxxxxxx>
---
man/virt-install.pod | 4 ++++
.../compare/virt-install-singleton-config-2.xml | 2 ++
tests/clitest.py | 2 +-
virtinst/cli.py | 16 ++++++++++++++++
virtinst/cpu.py | 18 ++++++++++++++++++
5 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/man/virt-install.pod b/man/virt-install.pod
index a030b3a..349e4e6 100644
--- a/man/virt-install.pod
+++ b/man/virt-install.pod
@@ -247,6 +247,10 @@ Example of specifying two NUMA cells. This will generate XML like:
</numa>
</cpu>
+=item B<--cpu host-passthrough,cache.mode=passthrough>
+
+Example of passing through the host cpu's cache information.
+
=back
Use --cpu=? to see a list of all available sub options. Complete details at L<http://libvirt.org/formatdomain.html#elementsCPU>
diff --git a/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml b/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml
index d7fbb49..658d0a4 100644
--- a/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml
+++ b/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml
@@ -83,6 +83,7 @@
<model>foobar</model>
<vendor>meee</vendor>
<topology sockets="2" cores="2" threads="2"/>
+ <cache level='3' mode='emulate'/>
<feature policy="force" name="x2apic"/>
<feature policy="force" name="x2apicagain"/>
<feature policy="require" name="reqtest"/>
@@ -237,6 +238,7 @@
<model>foobar</model>
<vendor>meee</vendor>
<topology sockets="2" cores="2" threads="2"/>
+ <cache level='3' mode='emulate'/>
<feature policy="force" name="x2apic"/>
<feature policy="force" name="x2apicagain"/>
<feature policy="require" name="reqtest"/>
diff --git a/tests/clitest.py b/tests/clitest.py
index 4f7f766..7e9e668 100644
--- a/tests/clitest.py
+++ b/tests/clitest.py
@@ -416,7 +416,7 @@ c.add_compare(""" \
c.add_compare("""--pxe \
--memory 512,maxmemory=1024 \
--vcpus 4,cores=2,threads=2,sockets=2 \
---cpu foobar,+x2apic,+x2apicagain,-distest,forbid=foo,forbid=bar,disable=distest2,optional=opttest,require=reqtest,match=strict,vendor=meee,cell.id=0,cell.cpus=1,2,3,cell.memory=1024,cell1.id=1,cell1.memory=256,cell1.cpus=5-8 \
+--cpu foobar,+x2apic,+x2apicagain,-distest,forbid=foo,forbid=bar,disable=distest2,optional=opttest,require=reqtest,match=strict,vendor=meee,cell.id=0,cell.cpus=1,2,3,cell.memory=1024,cell1.id=1,cell1.memory=256,cell1.cpus=5-8,cache.mode=emulate,cache.level=3 \
--metadata title=my-title,description=my-description,uuid=00000000-1111-2222-3333-444444444444 \
--boot cdrom,fd,hd,network,menu=off,loader=/foo/bar \
--idmap uid_start=0,uid_target=1000,uid_count=10,gid_start=0,gid_target=1000,gid_count=10 \
diff --git a/virtinst/cli.py b/virtinst/cli.py
index 900d185..7a8fd0c 100644
--- a/virtinst/cli.py
+++ b/virtinst/cli.py
@@ -1467,6 +1467,18 @@ class ParserCPU(VirtCLIParser):
else:
inst.add_feature(feature_name, policy)
+ def set_l3_cache_cb(self, inst, val, virtarg, can_edit):
+ cpu = inst
+
+ if can_edit:
+ cpu.set_l3_cache_mode()
+ try:
+ return cpu.cache[0]
+ except IndexError:
+ if not can_edit:
+ return None
+ raise
+
def _parse(self, inst):
# Convert +feature, -feature into expected format
for key, value in self.optdict.items():
@@ -1508,6 +1520,10 @@ ParserCPU.add_arg("cpus", "cell[0-9]*.cpus", can_comma=True,
ParserCPU.add_arg("memory", "cell[0-9]*.memory",
find_inst_cb=ParserCPU.cell_find_inst_cb)
+# Options for CPU.cache
+ParserCPU.add_arg("mode", "cache.mode", find_inst_cb=ParserCPU.set_l3_cache_cb)
+ParserCPU.add_arg("level", "cache.level", find_inst_cb=ParserCPU.set_l3_cache_cb)
+
###################
# --vcpus parsing #
diff --git a/virtinst/cpu.py b/virtinst/cpu.py
index 468853f..3925106 100644
--- a/virtinst/cpu.py
+++ b/virtinst/cpu.py
@@ -32,6 +32,18 @@ class _CPUCell(XMLBuilder):
memory = XMLProperty("./@memory", is_int=True)
+class CPUCache(XMLBuilder):
+ """
+ Class for generating <cpu> child <cache> XML
+ """
+
+ _XML_ROOT_NAME = "cache"
+ _XML_PROP_ORDER = ["mode", "level"]
+
+ mode = XMLProperty("./@mode")
+ level = XMLProperty("./@level", is_int=True)
+
+
class CPUFeature(XMLBuilder):
"""
Class for generating <cpu> child <feature> XML
@@ -107,6 +119,12 @@ class CPU(XMLBuilder):
self.add_child(obj)
return obj
+ cache = XMLChildProperty(CPUCache)
+ def set_l3_cache_mode(self):
+ obj = CPUCache(self.conn)
+ self.add_child(obj)
+ return obj
+
def copy_host_cpu(self):
"""
Enact the equivalent of qemu -cpu host, pulling all info
--
2.9.2
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